An Approach to Assess Solder Interconnect Degradation Using Digital Signal

Department of Human and Systems EngineeringDigital signals used in electronic systems require reliable data communication. It is necessary to monitor the system health continuously to prevent system failure in advance. Solder joints in electronic assemblies are one of the major failure sites under thermal, mechanical and chemical stress conditions during their operation. Solder joint degradation usually starts from the surface where high speed signals are concentrated due to the phenomenon referred to as the skin effect. Due to the skin effect, high speed signals are sensitive when detecting the early stages of solder joint degradation. The objective of the thesis is to assess solder joint degradation in a non-destructive way based on digital signal characterization. For accelerated life testing the stress conditions were designed in order to generate gradual degradation of solder joints. The signal generated by a digital signal transceiver was travelling through the solder joints to continuously monitor the signal integrity under the stress conditions. The signal properities were obtained by eye parameters and jitter, which represented the characteristics of the digital signal in terms of noise and timing error. The eye parameters and jitter exhibited significant increase after the exposure of the solder joints to the stress conditions. The test results indicated the deterioration of the signal integrity resulted from the solder joint degradation, and proved that high speed digital signals could serve as a non-destructive tool for sensing physical degradation. Since this approach is based on the digital signals used in electronic systems, it can be implemented without requiring additional sensing devices. Furthermore, this approach can serve as a proactive prognostic tool, which provides real-time health monitoring of electronic systems and triggers early warning for impending failure.ope

Effect of Jitter on the Settling Time of Mesochronous Clock Retiming Circuits

It is well known that timing jitter can degrade the bit error rate (BER) of receivers that recover the clock from input data. However, timing jitter can also result in an indefinite increase in the settling time of clock recovery circuits, particularly in low swing mesochronous systems. Mesochronous clock retiming circuits are required in repeaterless low swing on-chip interconnects. We first discuss how timing jitter can result in a large increase in the settling time of the clock recovery circuit. Next, the circuit is modelled as a Markov chain with absorbing states. The mean time to absorption of the Markov chain, which represents the mean settling time of the circuit, is determined. The model is validated through behavioural simulations of the circuit, the results of which match well with the model predictions. We consider circuits with (i) data dependent jitter, (ii) random jitter, and (iii) combination of both of them. We show that a mismatch between the strengths of up and down corrections of the retiming can reduce the settling time. In particular, a 10% mismatch can reduce the mean settling time by up to 40%. We leverage this fact toward improving the settling time performance, and propose useful techniques based on biased training sequences and mismatched charge pumps. We also present a coarse+fine clock retiming circuit, which can operate in coarse first mode, to reduce the settling time substantially. These fast settling retiming circuits are verified with circuit simulations.Comment: 23 pages, 40 figure

Phase and amplitude pre-emphasis techniques for low-power serial links

A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6Gb/s and 600mVpp output swing, a power budget of 3mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24mW, a budget of 4 mW/Gb/s

Data-dependent jitter and crosstalk-induced bounded uncorrelated jitter in copper interconnects

This paper resolves the jitter impairment of non-return-to-zero data in transmission lines. The limited bandwidth of the transmission line introduces data-dependent jitter. Crosstalk between neighbouring lines results in bounded uncorrelated jitter in the data eye. An analytical approach to representing data-dependent jitter and crosstalk-induced bounded uncorrelated jitter is presented. Comparison with jitter measurements of microstrip lines on FR4 board demonstrated accuracy to within 15% of the predictions for deterministic jitter

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

An exploration of synchronization solutions for parallel short-range optical interconnect in mesochronous systems

As a result of the increasing complexity of electronic chips, the bandwidths required for inter- and intra-chip communication are rapidly increasing. As optoelectronics provides high=bandwidth and high-density interconnection it is considered as a candidate for short-range interconnection. For such interconnections, situated at a low level in the systems hierarchy, the interconnect latency is extremely critical for the systems performance. This paper describes some methods for mesochronous synchronization, needed for such interconnections. It will be shown that it can be beneficial to use an additional optical link to transfer a synchronization signal. Such a reference signal can be used efficiently for phase detection, provided that the data skew is sufficiently small, and result in a decrease of the cost-per-link

Cancellation of crosstalk-induced jitter

A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-speed serial links. A simple model of electromagnetic coupling demonstrates the generation of crosstalk-induced jitter. The analysis highlights unique aspects of crosstalk-induced jitter that differ from far-end crosstalk. The model is used to predict the crosstalk-induced jitter in 2-PAM and 4-PAM, which is compared to measurement. Furthermore, the model suggests an equalizer that compensates for the data-induced electromagnetic coupling between adjacent links and is suitable for pre- or post-emphasis schemes. The circuits are implemented using 130-nm MOSFETs and operate at 5-10 Gb/s. The results demonstrate reduced deterministic jitter and lower bit-error rate (BER). At 10 Gb/s, the crosstalk-induced jitter equalizer opens the eye at 10^sup-12 BER from 17 to 45 ps and lowers the rms jitter from 8.7 to 6.3 ps

Optimization of an avionic VCSEL-based optical link through large signal characterization

Optical communication systems have been widely preferred for network communications, especially for Datacoms Local Area Network links. The optical technology is an excellent candidate for on-board systems due to the potential weight saving and EMC immunity. According to the short length of the link and a cost saving, Vertical Cavity Surface Emitting Laser (VCSEL) and multimode fiber are the best solution for gigabit systems. In this context, we propose a modeling of 850nm VCSEL based on the rate equations analysis to predict the optical interconnect performances (jitter, bit error rate). Our aim is to define the operation conditions of VCSEL under large signal modulation in order to maximize the Extinction Ratio (current IOFF below threshold) without affecting link performances. The VCSEL model is developed to provide large signal modulation response. Biasing below threshold causes stochastic turn-on delay. Fluctuations of this delay occur, due to the spontaneous emission. This leads to additional turn-on jitter. These stochastic effects are included in the model by adding the Langevin photon and electron noise sources. The VCSEL behavior under high-speed modulation is studied to observe the transient response and extract the resonance frequency, overshoot and turn-on delay. The associated jitter is evaluated with the standard deviation of the turn-on delay probability density function. Simulations of stochastic and deterministic jitters are realized under different conditions of modulation (OFF current levels). Comparing simulations with measurement results carried out on VCSEL and a short haul gigabit link validates the approach