Analysis for Design and Transformation of Autosynchronous State Machines

The paper deals with design and transformation methodology of autosynchronous state machines. The result is the design methodology for autosynchronous state machines with one-hot and Gray encodings. On the basis of their simulation models the timing parameters are defined and conditions for the correct behavior are pointed out. In order to simplify the design of these state machines, the transformation methodology of synchronous state machine in VHDL at RTL level to autosynchronous state machine is designed. These transformed state machines are compared in their chip area, power consumption and timing

SIMULATION AND IMPLEMENTATION ANALYSIS OF THE AUTOSYNCHRONOUS SUBSYSTEMS IN VLSI DEVICE

Práca sa zaoberá analýzou riešenia problémov synchrónnych číslicových obvodov. Výsledkom je vytvorenie metodiky pre návrh autosynchrónnych obvodov, definovanie ich časových parametrov na základe simulačných modelov a stanovenie podmienok pre ich správnu funkciu. Pre jednoduchý návrh týchto obvodov bola vytvorená metodika transformácie RTL popisu synchrónneho stavového automatu vo VHDL na autosynchrónny automat pri minimálnych zmenách. Nasleduje porovnanie transformovaných stavových automatov s ich originálnymi synchrónnymi predlohami v parametroch ako sú plocha čipu, prúdová spotreba a časovanie. Na záver práce je uvedené teoretické porovnanie rôznych typov synchronizácií (synchrónny, autosynchrónny, asynchrónny vo fundamentálnom režime, EAIC, Bundled-data, Dual-rail) na jednom príklade stavového automatu pri rovnakých technologických parametroch.This thesis focuses on problem-solution analysis of synchronous digital circuits; the results of which are autosynchronous circuit design methodology, timing parameter definitions based on simulation models and constraint settings. The RTL transformation of the synchronous state machine in VHDL language to an autosynchronous state machine was created with minimal modifications for the simple design of these circuits. Following this, a comparison of the transformed state machines with their synchronous originals in parameters such as chip area, current consumption and timing specification domain is introduced. The summation of this thesis displays a theoretical comparison of several types of synchronization (synchronous, autosynchronous, fundamental asynchronous, EAIC, Bundled-data, Dual-rail) which are presented on the single state machine example with the same technology parameters.