A Low-Voltage Electronically Tunable MOSFET-C Voltage-Mode First-Order All-Pass Filter Design

This paper presents a simple electronically tunable voltage-mode first-order all-pass filter realization with MOSFET-C technique. In comparison to the classical MOSFET-C filter circuits that employ active elements including large number of transistors the proposed circuit is only composed of a single two n-channel MOSFET-based inverting voltage buffer, three passive components, and one NMOS-based voltage-controlled resistor, which is with advantage used to electronically control the pole frequency of the filter in range 103 kHz to 18.3 MHz. The proposed filter is also very suitable for low-voltage operation, since between its supply rails it uses only two MOSFETs. In the paper the effect of load is investigated. In addition, in order to suppress the effect of non-zero output resistance of the inverting voltage buffer, two compensation techniques are also introduced. The theoretical results are verified by SPICE simulations using PTM 90 nm level-7 CMOS process BSIM3v3 parameters, where +/- 0.45 V supply voltages are used. Moreover, the behavior of the proposed filter was also experimentally measured using readily available array transistors CD4007UB by Texas Instruments

Operational Trans-Resistance Amplifier Based Tunable Wave Active Filter

In this paper, Operational Trans-Resistance Amplifier (OTRA) based wave active filter structures are presented. They are flexible and modular, making them suitable to implement higher order filters. The circuits implement the resistors using matched transistors, operating in linear region, making them well suited for IC fabrication. They are insensitive to parasitic input capacitances and input resistances due to the internally grounded input terminals of OTRA. As an application, a doubly terminated third order Butterworth low pass filter has been implemented, by substituting OTRA based wave equivalents of passive elements. PSPICE simulations are given to verify the theoretical analysis

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

0.5V 3rd-order Tunable gm-C Filter

This paper proposes a 3rd-order gm-C filter that operates with the extremely low voltage supply of 0.5V. The employed transconductor is capable for operating in an extremely low voltage power supply environment. A benefit offered by the employed transconductor is that the filter’s cut-off frequency can be tuned, through a dc control current, for relatively large ranges. The filter structure was designed using normal threshold transistors of a triple-well 0.13μm CMOS process and is operated under a 0.5V supply voltage; its behavior has been evaluated through simulation results by utilizing the Analog Design Environment of the Cadence software

High Input Impedance Voltage-Mode Biquad Filter Using VD-DIBAs

This paper deals with a single-input multiple-output biquadratic filter providing three functions (low-pass, high-pass and band-pass) based on voltage differencing differential input buffered amplifier (VD-DIBA). The quality factor and pole frequency can be electronically tuned via the bias current. The proposed circuit uses two VD-DIBAs and two grounded capacitors without any external resistors, which is suitable to further develop into an integrated circuit. Moreover, the circuit possesses high input impedance, providing easy voltage-mode cascading. It is shown that the filter structure can be easily extended to multi-input filter without any additional components, providing also all-pass and band-reject properties. The PSPICE simulation and experimental results are included, verifying the key characteristics of the proposed filter. The given results agree well with the theoretical presumptions

Realization of Low-Voltage Modified CBTA and Design of Cascadable Current-Mode All-Pass Filter

In this paper, a low voltage modified current backward transconductance amplifier (MCBTA) and a novel first-order current-mode (CM) all-pass filter are presented. The MCBTA can operate with ±0.9 V supply voltage and the total power consumption of MCBTA is 1.27 mW. The presented all-pass filter employs single MCBTA, a grounded resistor and a grounded capacitor. The circuit possesses low input and high output impedances which make it ideal for current-mode systems. The presented all-pass filter circuit can be made electronically tunable due to the bias current of the MCBTA. Non-ideal study along with simulation results are given for validation purpose. Further, an nth-order cascadable all-pass filter is also presented. It uses n MCBTAs, n grounded resistors and n grounded capacitors. The performance of the proposed circuits is demonstrated by using PSPICE simulations based on the 0.18 µm TSMC level-7 CMOS technology parameters

Electronically Tunable Resistorless Mixed Mode Biquad Filters

This paper presents a new realization of elec¬tronically tunable mixed mode (including transadmittance- and voltage-modes) biquad filter with single input, three outputs or three inputs, single output using voltage differ-encing transconductance amplifier (VDTA), a recently introduced active element. It can simultaneously realize standard filtering signals: low-pass, band-pass and high-pass or by selecting input terminals, it can realize all five different filtering signals: low-pass, band-pass, high-pass, band-stop and all-pass. The proposed filter circuit offers the following attractive feature: no requirement of invert-ing type input signal which is require no addition circuit, critical component matching conditions are not required in the design, the circuit parameters ω0 and Q can be set orthogonally or independently through adjusting the bias currents of the VDTAs, the proposed circuit employs two active and minimum numbers of passive components. Fur-thermore, this filter was investigated from the point of view of limited frequency range, stability conditions, effects of parasitic elements and effects of non-ideal and sensitivity. Thus, taking these effects and conditions into considera¬tion, working conditions and boundaries of this filter are determined. We also performed Monte Carlo, THD and noise analyses. Simulation results are given to confirm theoretical analyses

Log-domain All-pass Filter-based Multiphase Sinusoidal Oscillators

Log-domain current-mode multiphase sinusoidal oscillators based on all-pass filters are presented in this paper. The first-order differential equation is used for obtaining inverting and non-inverting all-pass filters. The proposed oscillators are realized by all-pass filters which can be electronically tuned their natural frequency and stage gain by adjusting the bias currents. Each all pass filter contains 10 NPN transistors and a grounded capacitor. The validated BJT model which used in SPICE simulation operated by a single power supply as low as 2.5 V. The frequency of oscillation can be controlled over four decades. The total harmonic distortions of these MSO at frequency 56.67 MHz and 54.44 MHz, obtained around 0.52% and 0.75%, respectively. The proposed circuits enable fully integrated in telecommunication systems and also suit to high-frequency applications. Nonideality studies and PSpice simulation results are included to confirm the theory

Tunable n-path notch filters for blocker suppression: modeling and verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm