All-Pass Sections with High Gain Opportunity

In this paper, two new circuits for realizing firstorder voltage-mode (VM) all-pass section (APS) with variable gain are presented. The first proposed filter uses a single differential difference current conveyor (DDCC), one grounded capacitor and three resistors. The second proposed filter consists of two DDCCs, three grounded resistors and one grounded capacitor. It provides highinput and low-output impedances and can provide high gain. Both of the proposed circuits do not require any element matching condition. Moreover, oscillator circuits with minimum number of active and passive elements are derived from the proposed APSs. The proposed circuits are tested experimentally or by simulation using SPICE program to confirm the theory

All-pass section with high gain opportunity

Minaei, Shahram (Dogus Author) -- Conference full title: 33rd International Conference on Telecommunications and Signal Processing, TSP 2010; Baden near Vienna; Austria; 17 August 2010 through 20 August 2010 -- Paper published in Radioengineering, 20 (1) pp. 3-9. Fultext accessible via https://hdl.handle.net/11376/1383In this paper, a new circuit configuration for realizing voltage-mode (VM) all-pass section (APS) is presented. The circuit is cascadable with other VM circuits because of its high input and low output impedances. It consists of two differential difference current conveyors (DDCCs), one grounded resistor and one grounded capacitor. The proposed circuit can be slightly changed by using two additional grounded resistors to provide high gain. Moreover, a quadrature oscillator with minimum number of active and passive elements is derived from the proposed APS. SPICE simulations are performed to verify the theory.Motorol

Voltage-Mode Multifunction Biquadratic Filters Using New Ultra-Low-Power Differential Difference Current Conveyors

This paper presents two low-power voltage-mode multifunction biquadratic filters using differential difference current conveyors. Each proposed circuit employs three differential difference current conveyors, two grounded capacitors and two grounded resistors. The low-voltage ultra-low-power differential difference current conveyor is used to provide low-power consumption of the proposed filters. By appropriately connecting the input and output terminals, the proposed filters can provide low-pass, band-pass, high-pass, band-stop and all-pass voltage responses at high-input terminals, which is a desirable feature for voltage-mode operations. The natural frequency and the quality factor can be orthogonally set by adjusting the circuit components. For realizing all the filter responses, no inverting-type input signal requirements as well as no component-matching conditional requirements are imposed. The incremental parameter sensitivities are also low. The characteristics of the proposed circuits are simulated by using PSPICE simulators to confirm the presented theory

Unity / variable gain voltage - mode / current - mode first - order all - pass filters using single Dual - X second generation current conveyor

In this paper, two new general topologies for realizing voltage-mode (VM)/current-mode (CM) first-order all-pass filter transfer functions (TFs) are presented. The proposed topologies use single dual-X second-generation current conveyor (DXCCII) and three impedances Z(1), Z(2) and Z(3). Based on the selection of Z(1), Z(2) and Z(3), new VM and CM all-pass filters with unity or variable gains are obtained. The proposed VM/CM filters have high-input/high-output impedances which provide easy cascading at their input/output terminals, respectively. Non-ideal gain and parasitic impedance effects, associated with actual DXCCII implementation, on the performance of the developed topologies are also included. Finally, simulation program with integrated circuit emphasis (SPICE) simulation results based on level 49, 0.25 mu m TSMC complementary metal-oxide-semiconductor (CMOS) technology parameters are given to confirm the theory

Supplementary First-Order All-Pass Filters with Two Grounded Passive Elements Using FDCCII

In this study, two novel first-order all-pass filters are proposed using only one grounded resistor and one grounded capacitor along with a fully differential current conveyor (FDCCII). There is no element-matching restriction. The presented all-pass filter circuits can be made electronically tunable due to the electronic resistors. Furthermore, the presented circuits enjoy high-input impedance for easy cascadability. The theoretical results are verified with SPICE simulations

Voltage-Mode All-Pass Filters Using Universal Voltage Conveyor and MOSFET-Based Electronic Resistors

The paper presents two novel realizations of voltage-mode first-order all-pass filters. Both circuits use single universal voltage conveyor (UVC), single capacitor, and two grounded resistors. Using the two NMOS transistors-based realizations of the electronic resistor with two symmetrical power supplies, presented all-pass filter circuits can be easily made electronically tunable. Proposed filter structures provide both inverting and non-inverting outputs at the same configuration simultaneously and they have high-input and low-output impedances that are desired for easy cascading in voltage-mode operations. The nonidealities of the proposed circuits are also analyzed and compared. The theoretical results of both circuits are verified by SPICE simulations using TSMC 0.35 μm CMOS process parameters. Based on the evaluation, the behavior of one of the circuits featuring better performance was also experimentally measured using the UVC-N1C 0520 integrated circuit

Current Conveyor All-Pass Sections: Brief Review and Novel Solution

This study relates to the review of an important analog electronic function in form of all-pass filter’s realization using assorted current conveyor types and their relative performances, which resulted in a novel solution based on a new proposed active element. The study encompasses notable proposals during last the decade or more, and provides a platform for a broader future survey on the topic for enhancing the knowledge penetration amongst the researchers in the specified field. A new active element named EXCCII (Extra-X second generation current conveyor) with buffered output is found in the study along with its use in a new first-order all-pass section, with possible realization using commercially available IC (AD-844) and results

Synthesis and monolithic integration of analogue signal processing networks

Data traffic of future 5G telecommunication systems is projected to increase 10 000-fold compared to current rates. 5G fronthaul links are therefore expected to operate in the mm-wave spectrum with some preliminary International Telecommunication Union specifications set for the 71-76 and 81-86 GHz bands. Processing 5 GHz as a single contiguous band in real-time, using existing digital signal processing (DSP) systems, is exceedingly challenging. A similar challenge exists in radio astronomy, with the Square Kilometer Array project expecting data throughput rates of 15 Tbits/s at its completion. Speed improvements on existing state-of-the-art DSPs of 2-3 orders of magnitude are therefore required to meet future demands. One possible mitigating approach to processing wideband data in real-time is to replace some DSP blocks with analog signal processing (ASP) equivalents, since analogue devices outperform their digital counterparts in terms of cost, power consumption and the maximum attainable bandwidth. The fundamental building block of any ASP is an all-pass network of prescribed response, which can always be synthesized by cascaded first- and second-order all-pass sections (with two cascaded first-order sections being a special case of the latter). The monolithic integration of all-pass networks in commercial CMOS and BiCMOS technology nodes is a key consideration for commercial adaptation of ASPs, since it supports mass production at reduced costs and operating power requirements, making the ASP approach feasible. However, this integration has presented a number of yet unsolved challenges. Firstly, the state-of-the-art methods for synthesizing quasi-arbitrary group delay functions using all-pass elements lack a theoretical synthesis procedure that guarantees minimum-order networks. In this work an analytically-based solution to the synthesis problem is presented that produces an all-pass network with a response approximating the required group delay to within an arbitrary minimax error. This method is shown to work for any physical realization of second-order all-pass elements, is guaranteed to converge to a global optimum solution without any choice of seed values as an input, and allows synthesis of pre-defined networks described either analytically or numerically. Secondly, second-order all-pass networks are currently primarily implemented in off-chip planar media, which is unsuited for high volume production. Component sensitivity, process tolerances and on-chip parasitics often make proposed on-chip designs impractical. Consequently, to date, no measured results of a dispersive on-chip second-order all-pass network suitable for ASP applications (delay Q-value (QD) larger than 1) have been presented in either CMOS or BiCMOS technology nodes. In this work, the first ever on-chip CMOS second-order all-pass network is proposed with a measured QD-value larger than 1. Measurements indicate a post-tuning bandwidth of 280 MHz, peak-to-nominal delay variation of 10 ns, QD-value of 1.15 and magnitude variation of 3.1 dB. An active on-chip mm-wave second-order all-pass network is further demonstrated in a 130 nm SiGe BiCMOS technology node with a bandwidth of 40 GHz, peak-to-nominal delay of 62 ps, QD-value of 3.6 and a magnitude ripple of 1.4 dB. This is the first time that measurement results of a mm-wave bandwidth second-order all-pass network have been reported. This work therefore presents the first step to monolithically integrating ASP solutions to conventional DSP problems, thereby enabling ultra-wideband signal processing on-chip in commercial technology nodes.Thesis (PhD)--University of Pretoria, 2018.Square Kilometer Array (SKA) project - postgraduate scholarshipElectrical, Electronic and Computer EngineeringPhDUnrestricte

CMOS IMAGE SENSORS FOR LAB-ON-A-CHIP MICROSYSTEM DESIGN

The work described herein serves as a foundation for the development of CMOS imaging in lab-on-a-chip microsystems. Lab-on-a-chip (LOC) systems attempt to emulate the functionality of a cell biology lab by incorporating multiple sensing modalidites into a single microscale system. LOC are applicable to drug development, implantable sensors, cell-based bio-chemical detectors and radiation detectors. The common theme across these systems is achieving performance under severe resource constraints including noise, bandwidth, power and size. The contributions of this work are in the areas of two core lab-on-a-chip imaging functions: object detection and optical measurements

Faculty of Engineering and Design. Research Review

STUDENTS AND ACADEMICS - This publication introduces you to the department or school and then each faculty member’s research areas, research applications, and their most recent activities. A comprehensive index can be found at the back of this publication to help guide you by specific areas of interest, as well as point out interdisciplinary topics and researchers. INDUSTRY LEADERS - This publication includes information regarding specific facilities, labs, and research areas of departments and schools as well as individual faculty members and researchers. A comprehensive index can be found at the back of this publication to help guide you by specific areas of interest, as well as point out interdisciplinary topics and researchers