Design of Digital Advanced Systems Based on Programmable System on Chip

This chapter fills up an advanced analysis of the state-of-the-art design in programmable SoC systems, giving a critical overall vision for every designer to implement real time operating systems and concurrent processing. The content of the chapter is divided in the next four main sections. First the evolution timeline of FPGA based systems is covered from its beginning until the last AP SoC chips. They are complex devices and it is necessary to have a well-known understanding to utilise them in the more efficient form possible. The more important advance digital systems structures and architectures are described. The embedded AP SoCs are analysed and main design methodologies are covered, focusing in hardware and co-design strategies. In this section is described the development of a real open source application that covers the fundamental parts in the design of a SoC system, ranging from the hardware development until the software design involving the embedded operating system and the user interface application. Finally, the system described in the last section is tested in a real scientific experiment and the results are evaluated

Control System Plant Simulator: A Framework For Hardware In The Loop Simulation

Control systems courses are common in undergraduate engineering programs. These courses focus on the design of the controller\u27s mathematical model but rarely have students explore the practical issues of implementing the controller. Real-time and embedded systems courses focus on these practical issues with students implementing controllers for simplified Hardware-in-the- Loop plants such as a digital servo motor. Designing controllers for complex physical plants is difficult due to prohibitive costs or the risk of accidents caused by faulty controllers. These difficulties can be overcome if a simulator replaces the hardware-in-the-loop physical plant. We designed and implemented the Control System Plant Simulator (CSPS) as a flexible framework for simulating plant models in control system implementation projects. The framework allows the user to model continuous and discrete plants defined as transfer functions or systems of state-space equations. This paper describes the design of the CSPS framework by highlighting the expansion and modification flexibility it provides with its operating system, non-real-time user interface, and physical device abstraction layers. The CSPS framework has advantages over commercial tools that can provide a hardware-in-the-loop plant simulation. The framework\u27s scope of usage is much narrower than the commercial tools making it easier to learn how to use and modify. Also, we distribute the framework as an open-source project making it readily available for use in any course without licensing, and ensuring that deeper and more complex customizations are possible. The paper concludes with a discussion of our successful experience using the framework in real-time systems course projects, and porting to two operating environments (standard Windows XP and Ardence RTX Real-Time Extensions for Windows), two user interfaces (C-based text, Visual Basic GUI), and two data acquisition devices (USB data acquisition, simulated multi-channel IO device)

Spacecraft attitude control using a smart control system

Traditionally, spacecraft attitude control has been implemented using control loops written in native code for a space hardened processor. The Naval Research Lab has taken this approach during the development of the Attitude Control Electronics (ACE) package. After the system was developed and delivered, NRL decided to explore alternate technologies to accomplish this same task more efficiently. The approach taken by NRL was to implement the ACE control loops using systems technologies. The purpose of this effort was to: (1) research capabilities required of an expert system in processing a classic closed-loop control algorithm; (2) research the development environment required to design and test an embedded expert systems environment; (3) research the complexity of design and development of expert systems versus a conventional approach; and (4) test the resulting systems against the flight acceptance test software for both response and accuracy. Two expert systems were selected to implement the control loops. Criteria used for the selection of the expert systems included that they had to run in both embedded systems and ground based environments. Using two different expert systems allowed a comparison of the real-time capabilities, inferencing capabilities, and the ground-based development environment. The two expert systems chosen for the evaluation were Spacecraft Command Language (SCL), and NEXTPERT Object. SCL is a smart control system produced for the NRL by Interface and Control Systems (ICS). SCL was developed to be used for real-time command, control, and monitoring of a new generation of spacecraft. NEXPERT Object is a commercially available product developed by Neuron Data. Results of the effort were evaluated using the ACE test bed. The ACE test bed had been developed and used to test the original flight hardware and software using simulators and flight-like interfaces. The test bed was used for testing the expert systems in a 'near-flight' environment. The technical approach, the system architecture, the development environments, knowledge base development, and results of this effort are detailed

Hybrid Linux System Modeling with Mixed-Level Simulation

Dissertação de mestrado integrado em Engenharia Electrónica Industrial e ComputadoresWe live in a world where the need for computer-based systems with better performances is growing fast, and part of these systems are embedded systems. This kind of systems are everywhere around us, and we use them everyday even without noticing. Nevertheless, there are issues related to embedded systems in what comes to real-time requirements, because the failure of such systems can be harmful to the user or its environment. For this reason, a common technique to meet real-time requirements in difficult scenarios is accelerating software applications by using parallelization techniques and dedicated hardware components. This dissertations’ goal is to adopt a methodology of hardware-software co-design aided by co-simulation, making the design flow more efficient and reliable. An isolated validation does not guarantee integral system functionality, but the use of an integrated co-simulation environment allows detecting system problems before moving to the physical implementation. In this dissertation, an integrated co-simulation environment will be developed, using the Quick EMUlator (QEMU) as a tool for emulating embedded software platforms in a Linux-based environment. A SystemVerilog Direct Programming Interface (DPI) Library was developed in order to allow SystemVerilog simulators that support DPI to perform co-simulation with QEMU. A library for DLL blocks was also developed in order to allow PSIMR to communicate with QEMU. Together with QEMU, these libraries open up the possibility to co-simulate several parts of a system that includes power electronics and hardware acceleration together with an emulated embedded platform. In order to validate the functionality of the developed co-simulation environment, a demonstration application scenario was developed following a design flow that takes advantage of the mentioned simulation environment capabilities.Vivemos num mundo em que a procura por sistemas computer-based com desempenhos cada vez melhores domina o mercado. Estamos rodeados por este tipo de sistemas, usando-os todos os dias sem nos apercebermos disso, sendo grande parte deles sistemas embebidos. Ainda assim, existem problemas relacionados com os sistemas embebidos no que toca aos requisitos de tempo-real, porque uma falha destes sistemas pode ser perigosa para o utilizador ou o ambiente que o rodeia. Devido a isto, uma técnica comum para se conseguir cumprir os requisitos de tempo-real em aplicações críticas é a aceleração de aplicações de software, utilizando técnicas de paralelização e o uso de componentes de hardware dedicados. O objetivo desta dissertação é adotar uma metodologia de co-design de hardwaresoftware apoiada em co-simulação, tornando o design flow mais eficiente e fiável. Uma validação isolada não garante a funcionalidade do sistema completo, mas a utilização de um ambiente de co-simulação permite detetar problemas no sistema antes deste ser implementado na plataforma alvo. Nesta dissertação será desenvolvido um ambiente de co-simulação usando o QEMU como emulador para as plataformas de software "embebido" baseadas em Linux. Uma biblioteca para SystemVerilog DPI foi desenvolvida, que permite a co-simulação entre o QEMU e simuladores de Register-Transfer Level (RTL) que suportem SystemVerilog. Foi também desenvolvida uma biblioteca para os blocos Dynamic Link Library (DLL) do PSIMR , de modo a permitir a ligação ao QEMU. Em conjunto, as bibliotecas desenvolvidas permitem a co-simulação de diversas partes do sistema, nomeadamente do hardware de eletrónica de potência e dos aceleradores de hardware, juntamente com a plataforma embebida emulada no QEMU.Para validar as funcionalidades do ambiente de co-simulação desenvolvido, foi explorado um cenário de aplicação que tem por base esse mesmo ambiente

Integration of RFID and Industrial WSNs to Create A Smart Industrial Environment

A smart environment is a physical space that is seamlessly embedded with sensors, actuators, displays, and computing devices, connected through communication networks for data collection, to enable various pervasive applications. Radio frequency identification (RFID) and Wireless Sensor Networks (WSNs) can be used to create such smart environments, performing sensing, data acquisition, and communication functions, and thus connecting physical devices together to form a smart environment. This thesis first examines the features and requirements a smart industrial environment. It then focuses on the realization of such an environment by integrating RFID and industrial WSNs. ISA100.11a protocol is considered in particular for WSNs, while High Frequency RFID is considered for this thesis. This thesis describes designs and implementation of the hardware and software architecture necessary for proper integration of RFID and WSN systems. The hardware architecture focuses on communication interface and AI/AO interface circuit design; while the driver of the interface is implemented through embedded software. Through Web-based Human Machine Interface (HMI), the industrial users can monitor the process parameters, as well as send any necessary alarm information. In addition, a standard Mongo database is designed, allowing access to historical and current data to gain a more in-depth understanding of the environment being created. The information can therefore be uploaded to an IoT Cloud platform for easy access and storage. Four scenarios for smart industrial environments are mimicked and tested in a laboratory to demonstrate the proposed integrated system. The experimental results have showed that the communication from RFID reader to WSN node and the real-time wireless transmission of the integrated system meet design requirements. In addition, compared to a traditional wired PLC system where measurement error of the integrated system is less than 1%. The experimental results are thus satisfactory, and the design specifications have been achieved

Leveraging new platforms to provide students with a realistic SoC design experience

Recently there have been a slew of digital design products released that promise to simplify the task of giving students a real-world System-on-Chip (SoC) design experience. These “programmable SoCs” from companies such as Xilinx, Cypress, and Altera combine modern multi-core ARM processors connected to an FPGA through a widely used SoC interconnect standard. This paper discusses a Real Time Embedded System Course I designed that uses the Xilinx Zynq platform to give students first-hand experience with modern System-on-Chip design methodologies and the challenges that designers face in both hardware and software bring-up for a modern IP-based design. The first portion of this paper discusses how students were trained to use the Zynq platform. The first weeks of the class were dedicated to teaching students the basics of real-time system and custom hardware design. Students used a Zynq-based port of Free-RTOS to learn about Real-time operating systems. Through a series of laboratory assignments, students are taught how to interface the RTOS with custom hardware that they place on the FPGA portion of the chip. The course material developed for this portion of the class will be posted online so that other educators may use it in their teaching. The second part of this paper discusses some of the projects proposed and completed by students, and any difficulties the students faced along the way. From two weeks into the class, students are asked to form groups of up to four and propose a final project. For their final project, students are required to design and build a complete working system of their choice. Their final project is required to make use of both the processor running RTOS and at least one custom IP block running on the FPGA. In the final section of this paper I examine student feedback for the course, and comment on some of the challenges I faced in integrating the Zynq PSoC platform, and its corresponding development tools, into the classroom