FPGA Implementation of Linear Frequency Modulation (LFM) Waveforms for Radar

The last few years have seen advances in radar signal generation and processing techniques with the development of powerful hardware and software. The key objective in designing a pulsed radar system is to attain a good range resolution and achieve maximum range detection. Pulse compression is a technique of signal processing that offers the advantages of greater range resolution capability as in case of short duration pulse and larger range detection capability of long duration pulse. Pulse compression using Linear Frequency Modulation (LFM) is a prevalent method in modern radar. In this proposed design, the LFM waveforms are generated using Direct Digital Synthesizer (DDS) technique. A carry save adder is used to optimize adder operations. The high speed adder architecture provides a greater system performance. This approach has been implemented on a Field Programmable Gate Array (FPGA) for the Radar applicationFPGA Implementation of Linear Frequency Modulation (LFM) Waveforms for Rada

Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS

We present a high performance low-power digital base-band architecture, specially designed for an energy optimized duty-cycled wake-up receiver scheme. Based on a careful wake-up beacon design, a structured wake-up beacon detection technique leads to an architecture that compensates for the implementation loss of a low-power wake-up receiver front-end at low energy and area costs. Design parameters are selected by energy optimization and the architecture is easily scalable to support various network sizes. Fabricated in 65nm CMOS, the digital base-band consumes 0.9uW (V_DD=0.37V) in sub-threshold operation at 250kbps, with appropriate 97% wake-up beacon detection and 0.04% false alarm probabilities. The circuit is fully functional at a minimum V_DD of 0.23V at f_max=5kHz and 0.018uW power consumption. Based on these results we show that our digital base-band can be used as a companion to compensate for front-end implementation losses resulting from the limited wake-up receiver power budget at a negligible cost. This implies an improvement of the practical sensitivity of the wake-up receiver, compared to what is traditionally reported.Comment: Submitted to IEEE Sensors Journa

Programmable Logic Devices in Experimental Quantum Optics

We discuss the unique capabilities of programmable logic devices (PLD's) for experimental quantum optics and describe basic procedures of design and implementation. Examples of advanced applications include optical metrology and feedback control of quantum dynamical systems. As a tutorial illustration of the PLD implementation process, a field programmable gate array (FPGA) controller is used to stabilize the output of a Fabry-Perot cavity

Test of a majority-based reversible (quantum) 4 bits ripple-carry adder in adiabatic calculation

Quantum computing and circuits are of growing interest and so is reversible logic as it plays an important role in the synthesis of circuits dedicated to quantum computation. Moreover, reversible logic provides an alternative to classical computing machines, that may overcome many of the power dissipation problems in the near future. As a proof of concept we designed and tested a reversible 4 bits ripple-carry adder based on a do-spy-undo structure. This paper presents some performances obtained with such a chip processed in standard 0.35 μm CMOS technology and used in real reversible calculation (in this study, computations are performed in both directions such that addition and subtraction are made reversibly with the same chip). We also discuss the superiority of using adiabatic signals over classical rectangular pulses when using dual-line pass-transistor logic gates. Adiabatic signals allow the signal energy stored on the various capacitances of the circuit to be redistributed rather than being dissipated as heat. Finally, we show that adiabatic signals allow to avoid calculation errors introduced by the use of conventional rectangular pulses and allow to drastically reduce the number of pulse resynchronization in large circuits. Index Terms—reversible computation, design, implementation, pass-transistor logic, ripple-carry adder, Spectre simulation, quantum computation, adiabatic signal, test and measuremen