Towards a design of HMO, an integrated hardware microcode optimizer

This paper discusses an algorithm for optimizing the density and parallelism of microcoded routines in micro-programmable machines. Besides presenting the algorithm itself, this research also analyzes the algorithm\u27s uses, design integration problems, architectural requirements, and adaptability to conventional machine characteristics. Even though the paper proposes a hardware implementation of the algorithm, the algorithm is viewed as an integral part of the entire microcode generation and usage process, from initial high-level input into a software microcode compiler down to machine-level execution of the resultant microcode on the host machine. It is believed that, by removing much of the traditionally time-consuming and machine-dependent microcode optimization from the software portion of this process, the algorithm can improve the overall process --Abstract, page ii

Designing HMO, an Integrated Hardware Microcode Optimizer

This Paper Discusses an Algorithm for Optimizing the Density and Parallelism of Micro coded Routines in Micro programmable Machines. Besides the Algorithm itself, the Algorithm\u27s Uses, Design Integration Problems, Architectural Requirements, and Adaptability to Conventional Machine Characteristics Are Also Discussed and Analyzed. Even Though the Paper Proposes a Hardware Implementation of the Algorithm, the Algorithm is Viewed as an Integral Part of the Entire Microcode Generation and Usage Process, from Initial High-Level Input into a Software Microcode Compiler Down to Machine-Level Execution of the Resultant Microcode on the Host Machine. It is Believed that, by Removing Much of the Traditionally Time-Consuming and Machine-Dependent Microcode Optimization from the Software Portion of This Process, the Algorithm Can Improve the overall Process

HMO, a hardware microcode optimizer

This Paper Discusses an Algorithm for Optimizing the Density and Parallelism of Micro coded Routines in Micro programmable Machines. Besides the Algorithm itself, the Algorithm\u27s Uses, Adaptability to Conventional Machine Characteristics, and Architectural Requirements Are Also Discussed and Analyzed. Even Though the Paper Proposes a Hardware Implementation of the Algorithm, the Algorithm is Viewed as an Integral Part of the Entire Microcode Generation and Usage Process, from Initial High-Level Input into a Software Microcode Compiler Down to Machine-Level Execution of the Resultant Microcode on the Host Machine. It is Believed that, by Removing Much of the Traditionally Time-Consuming and Machine-Dependent Microcode Optimization from the Software Portion of This Process, the Algorithm Can Improve the overall Process