Good trellises for IC implementation of viterbi decoders for linear block codes

This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered

A Synchronization Algorithm and Implementation for High-Speed Block Codes Applications

Block codes have trellis structures and decoders amenable to high speed CMOS VLSI implementation. For a given CMOS technology, these structures enable operating speeds higher than those achievable using convolutional codes for only modest reductions in coding gain. As a result, block codes have tremendous potential for satellite trunk and other future high-speed communication applications. This paper describes a new approach for implementation of the synchronization function for block codes. The approach utilizes the output of the Viterbi decoder and therefore employs the strength of the decoder. Its operation requires no knowledge of the signal-to-noise ratio of the received signal, has a simple implementation, adds no overhead to the transmitted data, and has been shown to be effective in simulation for received SNR greater than 2 dB

Map Algorithms for Decoding Linear Block codes Based on Sectionalized Trellis Diagrams

The MAP algorithm is a trellis-based maximum a posteriori probability decoding algorithm. It is the heart of the turbo (or iterative) decoding which achieves an error performance near the Shannon limit. Unfortunately, the implementation of this algorithm requires large computation and storage. Furthermore, its forward and backward recursions result in long decoding delay. For practical applications, this decoding algorithm must be simplified and its decoding complexity and delay must be reduced. In this paper, the MAP algorithm and its variations, such as Log-MAP and Max-Log-MAP algorithms, are first applied to sectionalized trellises for linear block codes and carried out as two-stage decodings. Using the structural properties of properly sectionalized trellises, the decoding complexity and delay of the MAP algorithms can be reduced. Computation-wise optimum sectionalizations of a trellis for MAP algorithms are investigated. Also presented in this paper are bi-directional and parallel MAP decodings

Implementation, verification and synthesis of the Gigabit Ethernet 1000BASE-T Physical Coding Sublayer

To meet the increasing demand for additional bandwidth requirements, high-speed connections are required to reduce traffic bottlenecks and improve performance on network systems. Gigabit Ethernet offers a cost-effective solution that is compatible with existing technologies to protect large investments in network infrastructure. IEEE standard 802.3ab 1000BASE-T (Gigabit Ethernet) physical layer standard offers this solution which upgrades networks to 1000Mbps data rates while maintaining the simplicity and manageability of the existing Ethernet networks, just as 100BASE-T Ethernet extended 10BASE-T Ethernet networks. The 1000BASE-T physical layer standard providing 1Gbps Ethernet signal transmission over four pairs of category 5 unshielded twisted pair (UTP) cable using the 5-level coding scheme. The Physical Coding Sublayer (PCS) of IEEE 802.3ab 1000BASE-T physical layer was developed and implemented. The behavioral modeling, functional modeling and simulation were done using Verilog HDL[Registered trademark symbol). Then, the PCS was synthesized using two process libraries: 0.35[Mu]m CMOS and 1.4[Mu]m CMOS. Two synthesis techniques, hierarchical optimization and hierarchical-flattening optimization, were explored to compare the area and timing tradeoffs between them. The automation of the synthesis was accomplished with the creation of synthesis script files. With these script files, the PCS can be synthesized automatically with any target library desired