Implementation, verification and synthesis of the Gigabit Ethernet 1000BASE-T Physical Coding Sublayer

Abstract

To meet the increasing demand for additional bandwidth requirements, high-speed connections are required to reduce traffic bottlenecks and improve performance on network systems. Gigabit Ethernet offers a cost-effective solution that is compatible with existing technologies to protect large investments in network infrastructure. IEEE standard 802.3ab 1000BASE-T (Gigabit Ethernet) physical layer standard offers this solution which upgrades networks to 1000Mbps data rates while maintaining the simplicity and manageability of the existing Ethernet networks, just as 100BASE-T Ethernet extended 10BASE-T Ethernet networks. The 1000BASE-T physical layer standard providing 1Gbps Ethernet signal transmission over four pairs of category 5 unshielded twisted pair (UTP) cable using the 5-level coding scheme. The Physical Coding Sublayer (PCS) of IEEE 802.3ab 1000BASE-T physical layer was developed and implemented. The behavioral modeling, functional modeling and simulation were done using Verilog HDL[Registered trademark symbol). Then, the PCS was synthesized using two process libraries: 0.35[Mu]m CMOS and 1.4[Mu]m CMOS. Two synthesis techniques, hierarchical optimization and hierarchical-flattening optimization, were explored to compare the area and timing tradeoffs between them. The automation of the synthesis was accomplished with the creation of synthesis script files. With these script files, the PCS can be synthesized automatically with any target library desired