20 research outputs found
Single-Strip Triangulation of Manifolds with Arbitrary Topology
Triangle strips have been widely used for efficient rendering. It is
NP-complete to test whether a given triangulated model can be represented as a
single triangle strip, so many heuristics have been proposed to partition
models into few long strips. In this paper, we present a new algorithm for
creating a single triangle loop or strip from a triangulated model. Our method
applies a dual graph matching algorithm to partition the mesh into cycles, and
then merges pairs of cycles by splitting adjacent triangles when necessary. New
vertices are introduced at midpoints of edges and the new triangles thus formed
are coplanar with their parent triangles, hence the visual fidelity of the
geometry is not changed. We prove that the increase in the number of triangles
due to this splitting is 50% in the worst case, however for all models we
tested the increase was less than 2%. We also prove tight bounds on the number
of triangles needed for a single-strip representation of a model with holes on
its boundary. Our strips can be used not only for efficient rendering, but also
for other applications including the generation of space filling curves on a
manifold of any arbitrary topology.Comment: 12 pages, 10 figures. To appear at Eurographics 200
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Hierarchical Large-scale Volume Representation with 3rd-root-of-2 Subdivision and Trivariate B-spline Wavelets
Multiresolution methods provide a means for representing data at multiple levels of detail. They are typically based on a hierarchical data organization scheme and update rules needed for data value computation. We use a data organization that is based on what we call subdivision. The main advantage of subdivision, compared to quadtree (n=2) or octree (n=3) organizations, is that the number of vertices is only doubled in each subdivision step instead of multiplied by a factor of four or eight, respectively. To update data values we use n-variate B-spline wavelets, which yield better approximations for each level of detail. We develop a lifting scheme for n=2 and n=3 based on the -subdivision scheme. We obtain narrow masks that provide a basis for out-of-core techniques as well as view-dependent visualization and adaptive, localized refinement
Characterization and modeling of PIDX parallel I/O for performance optimization
pre-printParallel I/O library performance can vary greatly in re- sponse to user-tunable parameter values such as aggregator count, file count, and aggregation strategy. Unfortunately, manual selection of these values is time consuming and dependent on characteristics of the target machine, the underlying file system, and the dataset itself. Some characteristics, such as the amount of memory per core, can also impose hard constraints on the range of viable parameter values. In this work we address these problems by using machine learning techniques to model the performance of the PIDX parallel I/O library and select appropriate tunable parameter values. We characterize both the network and I/O phases of PIDX on a Cray XE6 as well as an IBM Blue Gene/P system. We use the results of this study to develop a machine learning model for parameter space exploration and performance prediction
Global Static Indexing for Real-time Exploration of Very Large Regular Grids
In this paper we introduce a new indexing scheme for progressive traversal and visualization of large regular grids. We demonstrate the potential of our approach by providing a tool that displays at interactive rates planar slices of scalar field data with very modest computing resources. We obtain unprecedented results both in terms of absolute performance and, more importantly, in terms of scalability. On a laptop computer we provide real time interaction with a 2048 3 grid (8 Giga-nodes) using only 20MB of memory. On an SGI Onyx we slice interactively an 8192 3 grid ( tera-nodes) using only 60MB of memory. The scheme relies simply on the determination of an appropriate reordering of the rectilinear grid data and a progressive construction of the output slice. The reordering minimizes the amount of I/O performed during the out-of-core computation. The progressive and asynchronous computation of the output provides flexible quality/speed tradeoffs and a timecritical and interruptible user interface. 1