A low Complexity Wireless Gigabit Ethernet IFoF 60 GHz H/W Platform and Issues

6 pagesInternational audienceThis paper proposes a complete IFoF system architecture derived from simplified IEEE802.15.3c PHY layer proposal to successfully ensure near 1 Gbps on the air interface. The system architecture utilizes low complexity baseband processing modules. The byte/frame synchronization technique is designed to provide a high value of preamble detection probability and a very small value of the false detection probability. Conventional Reed-Solomon RS (255, 239) coding is used for Channel Forward Error Correction (FEC). Good communication link quality and Bit Error Rate (BER) results at 875 Mbps are achieved with directional antennas

VLSI Implementation of a Rate Decoder for Structural LDPC Channel Codes

AbstractThis paper proposes a low complexity low-density parity check decoder (LDPC) design. The design mainly accomplishes a message passing algorithm and systolic high throughput architecture. The typical mathematical calculations are based on the observation that nodes with high log likelihood ratio provide almost same information in every iteration and can be considered as stationary, we propose an algorithm in which the parity check matrix H is updated to a reduced complexity form every time a stationary node is encountered which results in lesser number of numerical computations in subsequent iterations. In this paper, we contemplately focuses on computational complexity and the decoder design significantly benefits from the high throughput point of view and the various improvisations introduced at various levels of abstraction in the decoder design. Threshold Controlled Min Sum Algorithm implements the LDPC decoder design for a code compliant with wired and wireless applications. A high performance LDPC decoder has been designed that achieves a throughput of 0.890 Gbps. The whole design of LDPC Decoder is designed, simulated and synthesized using Xilinx ISE 13.1 EDA Tool

Bridging the complexity gap in Tbps-achieving THz-band baseband processing

Recent advances in electronic and photonic technologies have allowed efficient signal generation and transmission at terahertz (THz) frequencies. However, as the gap in THz-operating devices narrows, the demand for terabit-per-second (Tbps)-achieving circuits is increasing. Translating the available hundreds of gigahertz (GHz) of bandwidth into a Tbps data rate requires processing thousands of information bits per clock cycle at state-of-the-art clock frequencies of digital baseband processing circuitry of a few GHz. This paper addresses these constraints and emphasizes the importance of parallelization in signal processing, particularly for channel code decoding. By leveraging structured sub-spaces of THz channels, we propose mapping bits to transmission resources using shorter code words, extending parallelizability across all baseband processing blocks. THz channels exhibit quasi-deterministic frequency, time, and space structures that enable efficient parallel bit mapping at the source and provide pseudo-soft bit reliability information for efficient detection and decoding at the receiver

Simulation framework for multigigabit applications at 60 GHz

This dissertation describes the implementation of a OFDM-based simulation framework for multigigabit applications at 60 GHz band over indoor multipath fading channels. The main goal of the framework is to provide a modular simulation tool designed for high data rate application in order to be easily adapted to a speci c standard or technology, such as 5G. The performance of OFDM using mmWave signals is severely a ected by non-linearities of the RF front-ends. This work analyses the impact of RF impairments in an OFDM system over multipath fading channels at 60 GHz using the proposed simulation framework. The impact of those impairments is evaluated through the metrics of BER, CFR, operation range and PSNR for residential and kiosk scenarios, suggested by the standard for LOS and NLOS. The presented framework allows the employment of 16 QAM or 64 QAM modulation scheme, and the length of the cyclic pre x extension is also con gurable. In order to simulate a realistic multipath fading channel, the proposed framework allows the insertion of a channel impulse response de ned by the user. The channel estimation can be performed either using pilot subcarriers or Golay sequence as channel estimation sequences. Independently of the channel estimation technique selected, frequency domain equalization is available through ZF approach or MMSE. The simulation framework also allows channel coding techniques in order to provide a more robustness transmission and to improve the link budget