A Theoretical Review of Topological Organization for Wireless Sensor Network

The recent decades have seen the growth in the fields of wireless communication technologies, which has made it possible to produce components with a rational cost of a few cubic millimeters of volume, called sensors. The collaboration of many of these wireless sensors with a basic base station gives birth to a network of wireless sensors. The latter faces numerous problems related to application requirements and the inadequate abilities of sensor nodes, particularly in terms of energy. In order to integrate the different models describing the characteristics of the nodes of a WSN, this paper presents the topological organization strategies to structure its communication. For large networks, partitioning into sub-networks (clusters) is a technique used to reduce consumption, improve network stability and facilitate scalability

A Theoretical Review of Topological Organization for Wireless Sensor Network

The recent decades have seen the growth in the fields of wireless communication technologies, which has made it possible to produce components with a rational cost of a few cubic millimeters of volume, called sensors. The collaboration of many of these wireless sensors with a basic base station gives birth to a network of wireless sensors. The latter faces numerous problems related to application requirements and the inadequate abilities of sensor nodes, particularly in terms of energy. In order to integrate the different models describing the characteristics of the nodes of a WSN, this paper presents the topological organization strategies to structure its communication. For large networks, partitioning into sub-networks (clusters) is a technique used to reduce consumption, improve network stability and facilitate scalability

Performance Modelling and Evaluation of Network On Chip Under Bursty Traffic. Performance evaluation of communication networks using analytical and simulation models in NOCs with Fat tree topology under Bursty Traffic with virtual channels.

Physical constrains of integrated circuits (commonly called chip) in regards to size and finite number of wires, has made the design of System-on-Chip (SoC) more interesting to study in terms of finding better solutions for the complexity of the chip-interconnections. The SoC has hundreds of Processing Elements (PEs), and a single shared bus can no longer be acceptable due to poor scalability with the system size. Networks on Chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems for complex SoCs. They consists of computational resources in the form of PE cores and switching nodes which allow PEs to communicate with each other. In the design and development of Networks on Chip, performance modelling and analysis has great theoretical and practical importance. This research is devoted to developing efficient and cost-effective analytical tools for the performance analysis and enhancement of NoCs with m-port n-tree topology under bursty traffic. Recent measurement studies have strongly verified that the traffic generated by many real-world applications in communication networks exhibits bursty and self-similar properties in nature and the message destinations are uniformly distributed. NoC's performance is generally affected by different traffic patterns generated by the processing elements. As the first step in the research, a new analytical model is developed to capture the burstiness and self-similarity characteristics of the traffic within NoCs through the use of Markov Modulated Poisson Process. The performance results of the developed model highlight the importance of accurate traffic modelling in the study and performance evaluation of NoCs. Having developed an efficient analytical tool to capture the traffic behaviour with a higher accuracy, in the next step, the research focuses on the effect of topology on the performance of NoCs. Many important challenges still remain as vulnerabilities within the design of NoCs with topology being the most important. Therefore a new analytical model is developed to investigate the performance of NoCs with the m-port n-tree topology under bursty traffic. Even though it is broadly proved in practice that fat-tree topology and its varieties result in lower latency, higher throughput and bandwidth, still most studies on NoCs adopt Mesh, Torus and Spidergon topologies. The results gained from the developed model and advanced simulation experiments significantly show the effect of fat-tree topology in reducing latency and increasing the throughput of NoCs. In order to obtain deeper understanding of NoCs performance attributes and for further improvement, in the final stage of the research, the developed analytical model was extended to consider the use of virtual channels within the architecture of NoCs. Extensive simulation experiments were carried out which show satisfactory improvements in the throughput of NoCs with fat-tree topology and VCs under bursty traffic. The analytical results and those obtained from extensive simulation experiments have shown a good degree of accuracy for predicting the network performance under different design alternatives and various traffic conditions.Libyan Ministry of Higher Educatio