0.13-µm CMOS tunable transconductor based on the body-driven gain boosting technique with application in Gm-C filters

We present a low-voltage low-power CMOS tunable transconductor exploiting body gain boosting to increase the small-signal output resistance. As a distinctive feature, the proposed scheme allows the OTA transconductance to be tuned via the current biasing the gain-boosting circuit. The proposed transconductor has been designed in a 0.13-µm CMOS technology and powered from a 1.2-V supply. To show a possible application, a 0.5-MHz tunable third order Chebyshev low pass filter suitable for the Ultra Low Power Bluetooth Standard has been designed. The filter simulations show that all the requirements of the chosen standard are met, with good performance in terms of linearity, noise and power consumption

High Gain Amplifier with Enhanced Cascoded Compensation

A two-stage CMOS operational amplifier with both, gain-boosting and indirect current feedback frequency compensation performed by means of regulated cascode amplifiers, is presented. By using quasi-floating-gate transistors (QFGT) the supply requirements, the number of capacitors and the size of the compensation capacitors respect to other Miller schemes are reduced. A prototype was fabricated using a 0.5 μm technology, resulting, for a load of 45 pF and supply voltage of 1.65 V, in open-loop-gain of 129 dB, 23 MHz of gain-bandwidth product, 60o phase margin, 675 μW power consumption and 1% settling time of 28 ns

Developing a framework of non-fatal occupational injury surveillance for risk control in palm oil mills

Non-fatal occupational injury (NFOI) and its risk factors have become a current global concern. The need of research towards the relationship between occupational injury and its risk factor is essential, to fulfil the purpose and setting the priority of implementing safety preventive approaches at workplace. This research intended to develop a framework of NFOI surveillance by using epidemiological data, noise exposure data and NFOI data among palm oil mills’ workers. A total of 420 respondents who assigned in operation and processing areas (OP) (n=333) and general or office workers (n=87) had voluntary participated in this research. A questionnaire session with respondents was held to obtain epidemiological data and NFOI information via validated questionnaire. Noise hazard monitoring was executed by using Sound Level Meter (SLM) for environmental noise monitoring and Personal Sound Dosimeter for personal noise monitoring. Gathered data were analysed in quantitative method by using statistical software IBM SPSS Statistic version 21 and a risk matrix table for injury risk rating evaluation. It was discovered that high noise exposure level (≥ 85 dB[A]) was significantly associated with non-fatal occupational injury among OP workers (φ=0.123, p<0.05) with OR=1.87 (95% CI, 1.080-3.235, p<0.05). Risk rating for reported NFOI was at moderate level, with minor cuts and scratches were the dominant type of injury (42.6%). Analysis of logistic regression indicated that working in shift, not wearing protective gloves, health problems such as shortness of breath and ringing in ears, and excessive noise level (≥ 85 dB[A]) were the risk factors of NFOI in palm oil mills among OP workers. A framework of nonfatal injury surveillance in palm oil mills was developed based on the findings with integration of risk management process and injury prevention principles. This framework is anticipated to help the management in decision making for preventive actions and early detection of occupational health effects among workers

A high-precision current-mode WTA-MAX circuit with multichip capability

This paper presents a circuit design technique suitable for the realization of winner-take-all (WTA), maximum (MAX), looser-take-all (LTA), and minimum (MIN) circuits. The technique presented is based on current replication and comparison. Traditional techniques rely on the matching of an N transistors array, where N is the number of system inputs. This implies that when N increases, as the size of the circuit and the distance between transistors will also increase, transistor matching degradation and loss of precision in the overall system performance will result. Furthermore, when multichip systems are required, the transistor matching is even worse and performance is drastically degraded. The technique presented in this paper does not rely on the proper matching of N transistors, but on the precise replication and comparison of currents. This can be performed by current mirrors with a limited number of outputs. Thus, N can increase without degrading the precision, even if the system is distributed among several chips. Also, the different chips constituting the system can be of different foundries without degrading the overall system precision. Experimental results that attest these facts are presented

Robust symmetric multiplication for programmable analog VLSI array processing

This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several blocks: a linearized transconductor, binary weighted current mirrors and a differential to single-ended current adder. This paper shows the advantages introduced using a linearized OTA-based multiplier. The circuit presented renders higher linearity and symmetry in the output current than a previously reported single-transistor multiplier. Its inclusion in an array processor based on CNN allows for a more accurate implementation of the processing model and a more robust weight distribution scheme than those found in previous designs.Office of Naval Research (USA) N-00014- 02-1-0884Ministerio de Ciencia y Tecnología TIC2003-09817-C02-0

FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).Ministerio de Economía y Competitividad TEC2015-71072-C3-3-RConsejería de Economía, Innovación y Ciencia. Junta de Andalucía P12-TIC-186

Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology

Over the last two decade, digital signal processing (DSP) has grown rapidly in electronic systems to provide more reconfigureability and programmability in the applications, compared to analog component, which allows easier design and test automation. Digital circuit usage is increasing because of scaling properties of very large scale integration (VLSI) processes. This has allowed new generation of digital circuit to attain higher speed, more functionality per chip, low power dissipation, lower cost. Analog world, analog to digital converter (ADC) are used to convert the signal from analog to digital domain. For interfacing with DSP sample and hold (S/H) circuit is a key building block in, and is often used in front end of the ADCs to relax their timing requirement. The function of S/H circuit is to take samples to its input signal and hold these samples in its output for some period of time. The analog circuits in low voltage and low power have assumed great significance due to mixed-mode design required for modern electronic gadgets that demand portability and little power consumption. The mixed mode circuit has existence of both analog and digital circuits on the same chip and it is possible to have low voltage digital circuit in modern scaled-down technologies. However the same is not always true with analog circuits due to the constrains of device noise level and threshold voltage (VT) of MOSFET. Thus for analog circuit to co-exist on the same substrate along with digital system and share same supply voltage, the operation of analog circuit in low voltage environment is essential. The objective of this research is to design a low-voltage, high-performance S/H circuit that will address the above problems. A typical switch capacitor S/H circuit needs amplifier, switches and capacitor. New amplifier have been designed by using the architecture of single stage fully differential folded cascode low voltage operation transconductance amplifier (OTA) which has high gain and speed; the gin boosting technique was used for purpose of increasing the gain of the OTA. This technique does not affect the speed of the single stage. The transmission gate switches using CMOS devices, which have higher linearity and higher speed over a single MOS switch, have been designed for use in the S/H circuit. The switches are operated by clock generator with two non overlapping clock signals having low rise and fall time offering low noise for the S/H circuit. The clock was designed with 77.17ps rise and fall time to reduce the errors of driving MOS switches which results in higher linearity. The S/H circuit was designed to operate with 1.8V supply voltage in 0.18um technology. The sampling rate is 40MSPS with spurious free dynamic range (SFDR) 65.7dB and SNR 70dB

A low-offset low-voltage CMOS Op Amp with rail-to-rail input and output ranges

A low voltage CMOS op amp is presented. The circuit uses complementary input pairs to achieve a rail-to-rail common mode input voltage range. Special attention has been given to the reduction of the op amp's systematic offset voltage. Gain boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain but also a significant reduction of the systematic offset voltag