6 research outputs found
GF(2^n) redundant representation using matrix embedding
By embedding a Toeplitz matrix-vector product (MVP) of dimension into a circulant MVP of dimension , where can be any nonnegative integer, we present a multiplication algorithm. This algorithm leads to a new redundant representation, and it has two merits: 1. The flexible choices of make it possible to select a proper such that the multiplication operation in ring ) can be performed using some asymptotically faster algorithms, e.g. the Fast Fourier Transformation (FFT)-based multiplication algorithm; 2. The redundant degrees, which are defined as , are smaller than those of most previous redundant representations, and in fact they are approximately equal to 2 for all applicable cases
Reconfigurable elliptic curve cryptography
Elliptic Curve Cryptosystems (ECC) have been proposed as an alternative to other established public key cryptosystems such as RSA (Rivest Shamir Adleman). ECC provide more security per bit than other known public key schemes based on the discrete logarithm problem. Smaller key sizes result in faster computations, lower power consumption and memory and bandwidth savings, thus making ECC a fast, flexible and cost-effective solution for providing security in constrained environments. Implementing ECC on reconfigurable platform combines the speed, security and concurrency of hardware along with the flexibility of the software approach.
This work proposes a generic architecture for elliptic curve cryptosystem on a Field Programmable Gate Array (FPGA) that performs an elliptic curve scalar multiplication in 1.16milliseconds for GF (2163), which is considerably faster than most other documented implementations. One of the benefits of the proposed processor architecture is that it is easily reprogrammable to use different algorithms and is adaptable to any field order. Also through reconfiguration the arithmetic unit can be optimized for different area/speed requirements. The mathematics involved uses binary extension field of the form GF (2n) as the underlying field and polynomial basis for the representation of the elements in the field. A significant gain in performance is obtained by using projective coordinates for the points on the curve during the computation process
Fault attacks and countermeasures for elliptic curve cryptosystems
In this thesis we have developed a new algorithmic countermeasures that protect elliptic curve computation by protecting computation of the finite binary extension field, against fault attacks. Firstly, we have proposed schemes, i.e., a Chinese Remainder Theorem based fault tolerant computation in finite field for use in ECCs, as well as Lagrange Interpolation based fault tolerant computation. Our approach is based on the error correcting codes, i.e., redundant residue polynomial codes and the use of first original approach of Reed-Solomon codes. Computation of the field elements is decomposed into parallel, mutually independent, modular/identical channels, so that in case of faults at one channel, errors will not distribute to other channels. Based on these schemes we have developed new algorithms, namely fault tolerant residue representation modular multiplication algorithm and fault tolerant Lagrange representation modular multiplication algorithm, which are immune against error propagation under the fault models that we propose: Random Fault Model, Arbitrary Fault Model, and Single Bit Fault Model. These algorithms provide fault tolerant computation in GF (2k) for use in ECCs. Our new developed algorithms where inputs, i.e., field elements, are represented by the redundant residue representation/ redundant lagrange representation enables us to overcome the problem if during computation one, or both coordinates x, y GF (2k) of the point P E/GF (2k) /Fk are corrupted. We assume that during each run of an attacked algorithm, in one single attack, an adversary can apply any of the proposed fault models, i.e., either Random Fault Model, or Arbitrary Fault Model, or Single Bit Fault Model. In this way more channels can be targeted, i.e., different fault models can be used on different channels. Also, our proposed algorithms can have masked errors and will not be immune against attacks which can create those kind of errors, but it is a difficult problem to counter masked errors, since any anti-fault attack scheme will have some masked errors. Moreover, we have derived conditions that inflicted error needs to have in order to yield undetectable faulty point on non-supersingular elliptic curve over GF(2k). Our algorithmic countermeasures can be applied to any public key cryptosystem that performs computation over the finite field GF (2k)
Efficient Implementation of Elliptic Curve Cryptography on FPGAs
This work presents the design strategies of an FPGA-based elliptic curve co-processor. Elliptic curve cryptography is an important topic in cryptography due to its relatively short key length and higher efficiency as compared to other well-known public key crypto-systems like RSA. The most important contributions of this work are: - Analyzing how different representations of finite fields and points on elliptic curves effect the performance of an elliptic curve co-processor and implementing a high performance co-processor. - Proposing a novel dynamic programming approach to find the optimum combination of different recursive polynomial multiplication methods. Here optimum means the method which has the smallest number of bit operations. - Designing a new normal-basis multiplier which is based on polynomial multipliers. The most important part of this multiplier is a circuit of size for changing the representation between polynomial and normal basis
Automated Design Space Exploration and Datapath Synthesis for Finite Field Arithmetic with Applications to Lightweight Cryptography
Today, emerging technologies are reaching astronomical proportions. For example, the Internet
of Things has numerous applications and consists of countless different devices using different
technologies with different capabilities. But the one invariant is their connectivity. Consequently,
secure communications, and cryptographic hardware as a means of providing them, are faced
with new challenges. Cryptographic algorithms intended for hardware implementations must be
designed with a good trade-off between implementation efficiency and sufficient cryptographic
strength. Finite fields are widely used in cryptography. Examples of algorithm design choices
related to finite field arithmetic are the field size, which arithmetic operations to use, how to
represent the field elements, etc. As there are many parameters to be considered and analyzed, an
automation framework is needed.
This thesis proposes a framework for automated design, implementation and verification of finite
field arithmetic hardware. The underlying motif throughout this work is âmath meets hardwareâ.
The automation framework is designed to bring the awareness of underlying mathematical
structures to the hardware design flow. It is implemented in GAP, an open source computer algebra
system that can work with finite fields and has symbolic computation capabilities. The framework
is roughly divided into two phases, the architectural decisions and the automated design genera-
tion. The architectural decisions phase supports parameter search and produces a list of candidates.
The automated design generation phase is invoked for each candidate, and the generated VHDL
files are passed on to conventional synthesis tools. The candidates and their implementation results
form the design space, and the framework allows rapid design space exploration in a systematic
way. In this thesis, design space exploration is focused on finite field arithmetic.
Three distinctive features of the proposed framework are the structure of finite fields, tower field
support, and on the fly submodule generation. Each finite field used in the design is represented as
both a field and its corresponding vector space. It is easy for a designer to switch between fields
and vector spaces, but strict distinction of the two is necessary for hierarchical designs. When an
expression is defined over an extension field, the top-level module contains element signals and
submodules for arithmetic operations on those signals. The submodules are generated with
corresponding vector signals and the arithmetic operations are now performed on the coordinates.
For tower fields, the submodules are generated for the subfield operations, and the design is generated
in a top-down fashion. The binding of expressions to the appropriate finite fields or vector spaces
and a set of customized methods allow the on the fly generation of expressions for implementation
of arithmetic operations, and hence submodule generation.
In the light of NIST Lightweight Cryptography Project (LWC), this work focuses mainly on small
finite fields. The thesis illustrates the impact of hardware implementation results during the design
process of WAGE, a Round 2 candidate in the NIST LWC standardization competition. WAGE
is a hardware oriented authenticated encryption scheme. The parameter selection for WAGE was
aimed at balancing the security and hardware implementation area, using hardware implementation
results for many design decisions, for example field size, representation of field elements, etc.
In the proposed framework, the components of WAGE are used as an example to illustrate different
automation flows and demonstrate the design space exploration on a real-world algorithm
Hardware processors for pairing-based cryptography
Bilinear pairings can be used to construct cryptographic systems with very desirable properties. A pairing performs a mapping on members of groups on elliptic and genus 2 hyperelliptic curves to an extension of the finite field on which the curves are defined. The finite fields must, however, be large to ensure adequate security. The complicated group structure of the curves and the expensive field operations result in time consuming computations that are an impediment to the practicality of pairing-based systems. The Tate pairing can be computed efficiently using the ÉłT method. Hardware architectures can be used to accelerate the required operations by exploiting the parallelism inherent to the algorithmic and finite field calculations. The Tate pairing can be performed on elliptic curves of characteristic 2 and 3 and on genus 2 hyperelliptic curves of characteristic 2. Curve selection is dependent on several factors including desired computational speed, the area constraints of the target device and the required security level. In this thesis, custom hardware processors for the acceleration of the Tate pairing are presented and implemented on an FPGA. The underlying hardware architectures are designed with care to exploit available parallelism while ensuring resource efficiency. The characteristic 2 elliptic curve processor contains novel units that return a pairing result in a very low number of clock cycles. Despite the more complicated computational algorithm, the speed of the genus 2 processor is comparable. Pairing computation on each of these curves can be appealing in applications with various attributes. A flexible processor that can perform pairing computation on elliptic curves of characteristic 2 and 3 has also been designed. An integrated hardware/software design and verification environment has been developed. This system automates the procedures required for robust processor creation and enables the rapid provision of solutions for a wide range of cryptographic applications