Spartan Daily, March 21, 1960

Volume 47, Issue 96https://scholarworks.sjsu.edu/spartandaily/4012/thumbnail.jp

Clock Generator Circuits for Low-Power Heterogeneous Multiprocessor Systems-on-Chip

In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core. For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed. The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed. The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications. Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies.In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können. Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren. Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

1974

History of Golf (1) The Nine Toughest Holes in the World (2) Stockie Madness (3) Bartender, One More Round for Pythium (3) Panel: 1973 Turf Problems in Review - 1974 Possible Remedies (A1-A12) Movement of Water to a Holding Pond (A13) Maintenance of Low Budget, Short Season Golf Courses (A16) Turfgrass Fertilization (A18) Determining Turfgrass Fertilizer Needs (A25) Shortage of Plant Food and How to Adjust to Supply and Cost (A29) Panel: Tricalcium Arsenate - Use and Abuse (A33-A46) Operating and Maintaining Municipal Golf Courses (A48) Maintenance of a High Budget Golf Course (A51) Trends in Agricultural Education and Where Are the Emphases (A58) Maintenance of Municipal Parks and Recreation Areas (A60) Maintenance of Grass Tennis Courts (A63) Transition from Natural to Artificial Turf (A67) Plant materials for Outlying Areas (A71) Care of University Grounds (A76) Maintenance of Industrial Sites (A79) Turfgrass Diseases and Systemic Fungicides (A81) A Look at the Future (A 84) Watering of Golf Course Turf (A92

Smokejumper Magazine, October 2002

This issue of the National Smokejumper Association (NSA) Smokejumper Magazine contains the following articles: Profiles Steve Rhodes, Adam Lauber, Larry Casey, Jim Rathbun, Jerry Howe, Murry Taylor and Jerry Linton, Death of Jimmy Pierce (John Culbertson), Smokejumpers and the CIA (Fred Donner), Interview with John Maclean (Steve Smith). Smokejumper Magazine continues Static Line, which was the original title of the NSA quarterly magazine.https://dc.ewu.edu/smokejumper_mag/1036/thumbnail.jp

Winona Daily News

https://openriver.winona.edu/winonadailynews/2061/thumbnail.jp

Smokejumper Magazine, January 2005

This issue of the National Smokejumper Association (NSA) Smokejumper Magazine contains the following articles: Smokejumper Magazine—How Does It Happen?, Smokejumpers to Ravens Part I continued in April 2005(Vietnam--Gene Hamner), Smokejumping Legacy in Alaska Ski Racing, Interviews with Smokejumpers from the 1940s. Smokejumper Magazine continues Static Line, which was the original title of the NSA quarterly magazine.https://dc.ewu.edu/smokejumper_mag/1045/thumbnail.jp

Space programs summary no. 37-54, volume 3 for the period 1 October to 30 November 1968. Supporting research and advanced development

Spacecraft propulsion, biological environment, guidance and control, electronic components, power supplies, propellants, instrumentation, telecommunication, and mission plannin