The roll back chip: hardware support for distributed simulation using time warp

Journal ArticleDistributed simulation offers an attractive means of meeting the high computational demands of discrete event simulation programs. The Time Warp mechanism has been proposed to ensure correct sequencing of events in distributed simulation programs without blocking processes unnecessarily. However, the overhead of state saving and rollback in Time Warp is one obstacle that may severely degrade performance. A special purpose hardware component, the rollback chip (RBC), is proposed to manage the state of a processor and provide an efficient rollback mechanism within a node of a parallel computer. The chip may be viewed as a special purpose memory management unit that lies on the data path between processor and memory. The algorithm implemented by the rollback chip is described, as well as extensions to the basic design. Implementation of the chip is briefly discussed. In addition to distributed simulation, the rollback chip may be used in other applications using the Time Warp mechanism, notably distributed database concurrency control

A KNOWLEDGE BASED SUPPORT TOOL FOR THE EARLY STAGES OF ELECTRONIC ENGINEERING DESIGN

A desire to produce a design support system for the early stages of electronic engineering design, has led to the conception of the Plymouth Engineer's Design Assistant (PEDA), pulling together experience from the three fields of computing, psychology and electronic engineering. The basic emphasis of this tool has been to use psychological techniques to analyze the cognitive aspects of designers in action and then make recommendations for design tool improvement. The results of the complementary psychological research, and other relevant literature are examined and potential avenues to realizing an improving design explored. A new idealized abstract representation of early electronic engineering is proposed, which is more in line witli the cognitive needs of designers, thus enabling the production of more capable design tools. The main points of the representation are discussed, and comparisons with other approaches and tools drawn. The abstract representation is then taken and used to form a specific implementation as the core to the PEDA tool. An overview of the PEDA tool is given, followed by a discussion regarding the important aspects of the implementation. Important issues and problems raised during the course of the research are discussed, together with suggestions for future work.THE UNIVERSITY OF READING and PLESSEY SEMI-CONDUCTORS, ROBOROUGH, PLYMOUT

論理シミュレーションとハードウェア記述言語に関する研究

京都大学0048新制・論文博士工学博士乙第7496号論工博第2471号新制||工||842(附属図書館)UT51-91-E273(主査)教授 矢島 脩三, 教授 津田 孝夫, 教授 田丸 啓吉学位規則第5条第2項該当Kyoto UniversityDFA

Test and Diagnosis of Integrated Circuits

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users, the manufacturing process is becoming finer and denser, making chips more prone to defects.The work presented in the HDR manuscript addresses the challenges of test and diagnosis of integrated circuits. It covers:- Power aware test;- Test of Low Power Devices;- Fault Diagnosis of digital circuits