First order model checking of w-Automata using multiway decision graphs

As the complexity of hardware digital systems increases, their correctness becomes a major concern. Traditional verification by simulation is infeasible to exhaustively test and guarantee correctness. More than a decade ago, however, formal verification has been introduced as complement technique to simulation. Formal methods establish that a design implementation satisfies its specification by mathematical reasoning. Among several techniques, model checking is one of the most successful technology, which is based on the exploration of the design state space. In this thesis, we propose a new model checking method based on the theory of }-automata and multiway decision graphs (MDGs). Unlike reduced ordered binary decision diagrams (ROBDDs), MDGs allow system models to be described using abstract state machines (ASMs) through abstract data sorts and uninterpreted function symbols, hence enabling the verification of larger designs independent of the datapath width. Given an ASM and a first-order linear time temporal logic property, the model checking problem proposed in this thesis is reduced to a language emptiness checking of an }-automaton that accepts all }-words produced by the system violating the property formula. The checking method comprises four steps: (1) transforming the first-order property into a propositional formula by constructing ASMs for the atomic formulas of the property; (2) generating an }-automaton from the negation of the transformed propositional formula; (3) computing the product of the generated automaton, the system model ASM and the constructed ASMs; and (4) applying a language emptiness checking algorithm on the product automaton. Three different checking algorithms have been developed, implemented, and proved correct in this thesis. To evaluate the performance of the proposed model checking method and implemented tool, we conducted several experimentations and case studies. We also compared the efficiency of our tool with an existing MDG regular model checking application, as well as with popular ROBDD-based automata model checking tools such as VIS. Our model checker was found to be outperforming the above tools

The verification of MDG algorithms in the HOL theorem prover

Formal verification of digital systems is achieved, today, using one of two main approaches: states exploration (mainly model checking and equivalence checking) or deductive reasoning (theorem proving). Indeed, the combination of the two approaches, states exploration and deductive reasoning promises to overcome the limitation and to enhance the capabilities of each. Our research is motivated by this goal. In this thesis, we provide the entire necessary infrastructure (data structure + algorithms) to define high level states exploration in the HOL theorem prover named as MDG-HOL platform. While related work has tackled the same problem by representing primitive Binary Decision Diagram (BDD) operations as inference rules added to the core of the theorem prover, we have based our approach on the Multiway Decision Graphs (MDGs). MDG generalizes ROBDD to represent and manipulate a subset of first-order logic formulae. With MDGs, a data value is represented by a single variable of an abstract type and operations on data are represented in terms of uninterpreted function. Considering MDGs instead of BDDs will raise the abstraction level of what can be verified using a state exploration within a theorem prover. The MDGs embedding is based on the logical formulation of an MDG as a Directed Formulae (DF). The DF syntax is defined as HOL built-in data types. We formalize the basic MDG operations using this syntax within HOL following a deep embedding approach. Such approach ensures the consistency of our embedding. Then, we derive the correctness proof for each MDG basic operator. Based on this platform, the MDG reachability analysis is defined in HOL as a conversion that uses the MDG theory within HOL. Then, we demonstrate the effectiveness of our platform by considering four case studies. Our obtained results show that this verification framework offers a considerable gain in terms of automation without sacrificing CPU time and memory usage compared to automatic model checker tools. Finally, we propose a reduction technique to improve MDGs model checking based on the MDG-HOL platform. The idea is to prune the transition relation of the circuits using pre-proved theorems and lemmas from the specification given at system level. We also use the consistency of the specifications to verify if the reduced model is faithful to the original one. We provide two case studies, the first one is the reduction using SAT-MDG of an Island Tunnel Controller and the second one is the MDG-HOL assume-guarantee reduction of the Look-Aside Interface. The obtained results of our approach offers a considerable gain in terms of heuristics and reduction techniques correctness as to commercial model checking; however a small penalty is paid in terms of CPU time and memory usag

A Design for verification approach using an embedding of PSL in AsmL

In this paper, we propose to integrate an embedding of Property Specification Language (PSL) in Abstract State Machines Language (AsmL) with a top–down design for verification approach in order to enable the model checking of large systems at the early stages of the design process. We provide a complete embedding of PSL in the ASM language AsmL, which allows us to integrate PSL properties as a part of the design. For verification, we propose a technique based on the AsmL tool that translates the code containing both the design and the properties into a finite state machine (FSM) representation. We use the generated FSM to run model checking on an external tool, here SMV. Our approach takes advantage of the AsmL language capabilities to model designs at the system level as well as from the power of the AsmL tool in generating both C# code and FSMs from AsmL models. We applied our approach on the PCI-X bus standard, which AsmL model was constructed from the informal standard specifications and a subsequent UML model. Experimental results on the PCI-X bus case study showed a superiority of our approach to conventional verification

Integrating SAT with MDG for Efficient Invariant Checking

Multiway Decision Graph (MDG) is a canonical representation of a subset of many-sorted first-order logic. It generalizes the logic of equality with abstract types and uninterpreted function symbols. The area of Satisfiability (SAT) has been the subject of intensive research in recent years, with significant theoretical and practical contributions. From a practical perspective, a large number of very effective SAT solvers have recently been proposed, most of which based on improvements made to the original Davis-Putnam algorithm. Local search algorithms have allowed solving extremely large satisfiable instances of SAT. The combination between various verification methodologies will enhance the capabilities of each and overcome their limitations. In this thesis, we introduce a methodology and propose a new design verification tool integrating MDG and SAT, to check the safety of a design by invariant checking. Using MDG to encode the set of states provide powerful mean of abstraction. We use SAT solver searching for paths of reachable states violating the property under certain encoding constraints. In addition, we also introduce an automated conversion-verification methodology to convert a Directed Formula (DF) into Conjunctive Normal Form (CNF) formula that can be fed to a SAT solver. The formal verification of this conversion is conducted within the HOL theorem prover. Finally, we implement and conduct experiment on some examples along with a case study to show the correctness and the efficiency of our approach

Identification of Soft-Error at Gate Level

Due to shrinking feature size and significant reduction in noise margins, as we are moving into very deep sub-micron technology, circuits have become more susceptible to manufacturing defects, noise-related transient faults and interference from radiation. Traditionally, soft errors have been a much greater concern in memories than in logic circuits. However, due to technology scaling, logic circuits have become equally susceptible to soft errors. Moreover, enhanced usage of commercial off the shelf (COTS) electronic components for avionics has also increased the importance of analyzing soft errors in hardware circuits. Conventionally, understanding soft error glitches requires circuit level modeling, which requires information available only at late stages in the design flow. Instead of this approach some researchers have produced modeling techniques using Reduced Order Binary Decision Diagrams (ROBDD) and Algebraic Decision Diagrams (ADD), which does allow analyzing soft error at an earlier stage in design flow. In this thesis, a new methodology for modeling soft errors glitch propagation path using Multiway Decision Graphs is introduced. This modeling technique is applicable on both combinational and asynchronous circuits. The proposed glitch propagation path modeling technique jointly takes care of logical and electrical masking. Our methodology involves new ways of injecting glitches including glitch injection in feedback paths of asynchronous circuits. This work presents a complete framework to exhaustively provide all the possible sequences of signals that lead to the possibility of glitch propagation to the primary output in combinational and asynchronous circuits. In addition, a new tool is developed based on the proposed methodology called Soft Error Glitch-Propagating Path Finder (SEGP-Finder) to automate the identification of these sequences of signals. This work helps designers identify the vulnerable circuit paths at the logic abstraction level. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of possibilities. By applying our methodology on different combinational and asynchronous circuits an improvement in terms of possible-fault injection vectors is observed. As an example, approximately 8% of all the possible input vectors and sequences is required for obtaining exhaustive glitch propagation path identification in a representative implementation of a bundled data asynchronous circuit. To the best of our knowledge, this is the first time MDG based decision diagram based soft error identification approach is proposed for combinational and asynchronous circuits

Assessing data quality in the community health worker (CHW) program in Eastern province, Rwanda

Background In order to achieve global development goals, the international community has called for the use of community health workers (CHWs) to deliver important health services. CHWs are routinely collecting large amounts of information. As program managers use these data to monitor and evaluate community-based activities, achieving and maintaining high data quality is critical. Objectives Measuring: 1) data accuracy of household registers compared to household interviews and client records in one district; 2) data reliability of monthly village reports compared to program registers in three districts; and 3) CHW and program factors related to data accuracy and reliability. Methods We used lot quality assurance sampling (LQAS) to determine data quality May 2011- June 2012. We randomly sampled: 1) six CHWs per cell, six households per CHW and classified cells as having ‘poor’ or ‘good’ accuracy for household registers based on five health indicators and a composite one, calculating point estimates by health center; and 2) 19 villages per health center classifying health centers as having ‘poor’ or ‘good’ reliability for village reports for three program indicators and a composite one, calculating point estimates by district. We administered a structured interview to CHWs in three districts measuring CHW and program factors, using logistic regression to measure associations with binary dependent variables data accuracy and reliability. Results Accuracy of household data varied by health center: point estimates were 61-72% for the composite indicator. Data reliability was poor across all districts: point estimates for the composite indicator were 26-60%. CHW having logged a visit to the household in the last month in the household register significantly increased odds of accurate data (OR: 1.71; 95%CI: 1.22, 2.39). The more sick children seen by CHWs significantly worsened data reliability: for four or more sick children versus none, OR: 0.283; 95%CI: 0.180, 0.445. Conclusions Community level data quality is variable in Rwanda, with CHWs generally able to collect data accurately, but not aggregate it correctly due to some program factors. To ensure dependable utilization of information by program managers, we recommend improved supervision and training and LQAS-based routine data quality assessments

Exploration of Knowledge and Skills Development among Community Health Workers in Rwanda

Community Health Workers (CHWs) are individuals who are selected and trained to provide healthcare services in the community. To be effective, they need ongoing training opportunities to gain knowledge and skills to perform their tasks. This study used descriptive qualitative methods to explore how Animatrice de Santé Maternelle (ASM)-CHWs working in select regions of Rwanda gained and enhanced their knowledge and skills to support maternal and newborn health care. Thematic analysis was used to analyze data from 110 ASM-CHWs and ten supervisors of CHWs. The analysis yielded two main themes. 1) Formalized training among CHWs, which included the subthemes of didactic training workshops, supervision, and monthly meetings. 2) Informalized training, with subthemes of informal peer to peer mentorship, learning as an ongoing process, moving toward formalized peer to peer mentorship model with its benefits, way to move forward, and challenges of peer to peer mentorship model. Adequate training of CHWs is crucial to the success of the program. However, training of CHWs was hampered by the unavailability of funds. Thus, peer to peer formal mentorship could serve as a learning strategy to reinforce the training of CHWs. Keywords: Community health worker, training strategie