Impact of Device Parameteres of Triple Gate SOI-FINFET on the Performance of CMOS Inverter at 22NM

A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the down scaling of the gate oxide thickness due to higher gate leakage current and gate capacitance

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

Ultra-low Power FinFET SRAM Cell with improved stability suitable for low power applications

In this paper, a new 11T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at sub-threshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV. At sub-threshold operation also it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Also, impact of process variation on cell stability is discussed

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

Electromechanical Switches Fabricated by Electrophoretic Deposition of Single Wall Carbon Nanotube Films

University of Minnesota Ph.D. dissertation.August 2015. Major: Electrical/Computer Engineering. Advisor: Stephen Campbell. 1 computer file (PDF); xi, 110 pages.Power dissipation is a critical problem of CMOS devices especially for mobile applications. Many efforts have been made to solve the problem, but there are still major issues associated with scaling the device size. Micro electromechanical (MEMS) and nano electromechanical (NEMS) devices are one candidate to solve the problems because of their excellent standby leakage. However, the switches have a tradeoff between low operating power and high device speed. Suspended beams with low mass density and good mechanical properties provide a way to optimize the device. Carbon nanotubes (CNTs) have the low mass density and excellent mechanical properties to enable high performance MEMS/NEMS devices. However, the high temperature required for the direct synthesis for CNTs makes it difficult for them to be compatible with a substrate containing transistors. Therefore, continuous film deposition techniques are investigated with low temperature (< 300 C). Electrophoretic deposition (EPD) is a simple and versatile processing method to deposit carbon nanotubes on the substrate at room temperature. The movement of the charged CNTs in suspension occurs by an applied electric field. The deposited CNT film thickness can be controlled through the applied voltage and process time. We demonstrate the use of an EPD process to deposit various thicknesses of CNT films. Film thicknesses are studied as a function of, deposition time, electric field strength, and suspension concentration. The deposition mechanism of the EPD process for carbon nanotube layers was explained with experimental data. We determined the film mass density and electrical/optical properties of SWCNT films. Rutherford backscattering spectroscopy was used to determine the film mass density. Films created in this manner had a mass density that varies with thickness from 0.12 to 0.54 g/cm3 and a resistivity of 2.1410-3 Ω∙cm. For the mechanical property measurements, we describe a technique to fabricate free-standing thin films using modified Langmuir-Blodgett method. Then we extracted the Young’s modulus of the film from the load-displacement data from nanoindentation using the appropriate modeling. The Young’s modulus had a range of 4.72 to 5.67 GPa, independent of deposited thickness. We fabricated two-terminal fixed beam switches with SWCNT thin films using the EPD process. Device pull-in voltages under 1V were achieved by decreasing the air-gap. The pull-in voltages were compared with the calculated results using the device geometry and extracted Young’s modulus from nanoindentation. Generally good agreement was observed. Also, we found a range of 2.4 to 3.5 MHz resonant frequency. However, we encountered several problems with the device including a gradual turn-on, hysteresis between pull-in and pull-out voltage, changes in the pull-in voltages with repeated on-off cycling, and early failure due to moisture absorption during testing in the air. Mechanisms for these observations are postulated. Further work is needed to improve device performance and reliability