Impact of self-heating on the statistical variability in bulk and SOI FinFETs

In this paper for the first time we study the impact of self-heating on the statistical variability of bulk and SOI FinFETs designed to meet the requirements of the 14/16nm technology node. The simulations are performed using the GSS ‘atomistic’ simulator GARAND using an enhanced electro-thermal model that takes into account the impact of the fin geometry on the thermal conductivity. In the simulations we have compared the statistical variability obtained from full-scale electro-thermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electro-thermal simulations. The combined effects of line edge roughness and metal gate granularity are taken into account. The distributions and the correlations between key figures of merit including the threshold voltage, on-current, subthreshold slope and leakage current are presented and analysed

Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability

In this paper we illustrate how by using advanced atomistic TCAD tools the interplay between long-range process variation and short-range statistical variability in FinFETs can be accurately modelled and simulated for the purposes of Design-Technology Co-Optimization (DTCO). The proposed statistical simulation and compact modelling methodology is demonstrated via a comprehensive evaluation of the impact of FinFET variability on SRAM cell stability

A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology

The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value

Inverse scaling trends for charge-trapping-induced degradation of FinFETs performance

In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several regimes of conduction-from subthreshold to ON-state. Contrary to what is expected for planar MOSFETs, we show that the trap impact decreases with scaling down the FinFET size and the applied gate voltage. By comparing drift-diffusion with nonequilibrium Green functions simulations, we show that quantum effects in the charge distribution and transport can reduce or amplify the impact of discrete traps in simulation of reliability resilience of scaled FinFETs

Statistical variability and reliability in nanoscale FinFETs

A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics

Dopant metrology in advanced FinFETs

Ultra-scaled FinFET transistors bear unique fingerprint-like device-to-device differences attributed to random single impurities. This paper describes how, through correlation of experimental data with multimillion atom tight-binding simulations using the NEMO 3-D code, it is possible to identify the impurity's chemical species and determine their concentration, local electric field and depth below the Si/SiO$_{\mathrm{2}}$ interface. The ability to model the excited states rather than just the ground state is the critical component of the analysis and allows the demonstration of a new approach to atomistic impurity metrology.Comment: 6 pages, 3 figure

A device-level characterization approach to quantify the impacts of different random variation sources in FinFET technology

A simple device-level characterization approach to quantitatively evaluate the impacts of different random variation sources in FinFETs is proposed. The impacts of random dopant fluctuation are negligible for FinFETs with lightly doped channel, leaving metal gate granularity and line-edge roughness as the two major random variation sources. The variations of Vth induced by these two major categories are theoretically decomposed based on the distinction in physical mechanisms and their influences on different electrical characteristics. The effectiveness of the proposed method is confirmed through both TCAD simulations and experimental results. This letter can provide helpful guidelines for variation-aware technology development

HAADF-STEM block-scanning strategy for local measurement of strain at the nanoscale

Lattice strain measurement of nanoscale semiconductor devices is crucial for the semiconductor industry as strain substantially improves the electrical performance of transistors. High resolution scanning transmission electron microscopy (HR-STEM) imaging is an excellent tool that provides spatial resolution at the atomic scale and strain information by applying Geometric Phase Analysis or image fitting procedures. However, HR-STEM images regularly suffer from scanning distortions and sample drift during image acquisition. In this paper, we propose a new scanning strategy that drastically reduces artefacts due to drift and scanning distortion, along with extending the field of view. The method allows flexible tuning of the spatial resolution and decouples the choice of field of view from the need for local atomic resolution. It consists of the acquisition of a series of independent small subimages containing an atomic resolution image of the local lattice. All subimages are then analysed individually for strain by fitting a nonlinear model to the lattice images. The obtained experimental strain maps are quantitatively benchmarked against the Bessel diffraction technique. We demonstrate that the proposed scanning strategy approaches the performance of the diffraction technique while having the advantage that it does not require specialized diffraction cameras

hp-finite element method for simulating light scattering from complex 3D structures

Methods for solving Maxwell's equations are integral part of optical metrology and computational lithography setups. Applications require accurate geometrical resolution, high numerical accuracy and/or low computation times. We present a finite-element based electromagnetic field solver relying on unstructured 3D meshes and adaptive hp-refinement. We apply the method for simulating light scattering off arrays of high aspect-ratio nano-posts and FinFETs