18,379 research outputs found
Bit-stream adders and multipliers for tri-level sigma-delta modulators
We propose both adder and multiplier circuits for bit-stream signal processing customized for tri-level sigma-delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy. © 2007 IEEE.published_or_final_versio
An Implementation of List Successive Cancellation Decoder with Large List Size for Polar Codes
Polar codes are the first class of forward error correction (FEC) codes with
a provably capacity-achieving capability. Using list successive cancellation
decoding (LSCD) with a large list size, the error correction performance of
polar codes exceeds other well-known FEC codes. However, the hardware
complexity of LSCD rapidly increases with the list size, which incurs high
usage of the resources on the field programmable gate array (FPGA) and
significantly impedes the practical deployment of polar codes. To alleviate the
high complexity, in this paper, two low-complexity decoding schemes and the
corresponding architectures for LSCD targeting FPGA implementation are
proposed. The architecture is implemented in an Altera Stratix V FPGA.
Measurement results show that, even with a list size of 32, the architecture is
able to decode a codeword of 4096-bit polar code within 150 us, achieving a
throughput of 27MbpsComment: 4 pages, 4 figures, 4 tables, Published in 27th International
Conference on Field Programmable Logic and Applications (FPL), 201
A case study for NoC based homogeneous MPSoC architectures
The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processo
Empowering parallel computing with field programmable gate arrays
After more than 30 years, reconfigurable computing has grown from a concept to a mature field of science and technology. The cornerstone of this evolution is the field programmable gate array, a building block enabling the configuration of a custom hardware architecture. The departure from static von Neumannlike architectures opens the way to eliminate the instruction overhead and to optimize the execution speed and power consumption. FPGAs now live in a growing ecosystem of development tools, enabling software programmers to map algorithms directly onto hardware. Applications abound in many directions, including data centers, IoT, AI, image processing and space exploration. The increasing success of FPGAs is largely due to an improved toolchain with solid high-level synthesis support as well as a better integration with processor and memory systems. On the other hand, long compile times and complex design exploration remain areas for improvement. In this paper we address the evolution of FPGAs towards advanced multi-functional accelerators, discuss different programming models and their HLS language implementations, as well as high-performance tuning of FPGAs integrated into a heterogeneous platform. We pinpoint fallacies and pitfalls, and identify opportunities for language enhancements and architectural refinements
Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems
In this paper, a field programmable gate array (FPGA) implementation of a linear minimum mean square error (LMMSE) detector is considered for MIMO-OFDM systems. Two square root free algorithms based on QR decomposition (QRD) are introduced for the implementation of LMMSE detector. Both algorithms are based on QRD via Givens rotations, namely coordinate rotation digital computer (CORDIC) and squared
Givens rotation (SGR) algorithms. Linear and triangular shaped array architectures are considered to exploit the parallelism in the computations. An FPGA hardware implementation is presented and computational complexity of each implementation is evaluated and compared.ElekrobitNokiaTexas InstrumentsNational Technology Agency of FinlandTeke
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