Timing models for high-level synthesis

In this paper, we describe a timing model for clock estimation during high-level synthesis. In order to obtain realistic timing estimates, the proposed model considers all delay elements, including datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices must be rapidly and incrementally calculated

Integration of behavioral and layout synthesis : a chip synthesis approach

Chip synthesis deals with the transformation of a behavioral description into a fabricated chip. Typically, chip synthesis is carried out in three stages: behavioral, logic/sequential and layout synthesis. Since chip synthesis involves a multi-level synthesis task, integration and coordination of tasks for all levels of synthesis is the essential issue.This dissertation addresses a chip synthesis paradigm and describes the key issues with regard to the integration of behavioral and layout synthesis for chip design. In order to successfully integrate all tasks in the chip synthesis process, a finite-state machine with a datapath (FSMD) design model and a sliced-layout architecture have been developed for chip synthesis. Using the sliced-layout architecture, a partitioning-based layout synthesis method and system have been developed to synthesize layout from generalized register-transfer (RT) netlists. In addition, based on the FSMD and the sliced-layout architecture, area and timing models are developed for behavioral synthesis. To incorporate layout information into behavioral synthesis, a unified representation is developed for behavioral synthesis. Using the unified representation and layout model, a layout-driven unit-binding approach is presented. Several sets of experiments were performed to validate the proposed approaches including the layout-synthesis method, the layout model and the layout-driven unit-binding task

Back-annotation for interactive data path synthesis

In order to take into account physical design effects, a designer needs a feedback mechanism during interactive data path synthesis. In this paper, we propose a hypergraph model and a back-annotation algorithm which provide a feedback mechanism for back-annotation from physical designs to behavioral descriptions. Given a control data flow graph and its structural design, this back-annotation technique cannot only evaluate the design quality but can also feedback the delay to each edge and node in the graph. Therefore, a designer can identify the critical paths and improve the design. The hypergraph model and the back-annotation algorithm allow us to bridge the gap between the behavioral description and the physical design

Layout area models for high-level synthesis

Traditionally, the common cost functions, the number of functional units, registers and selector inputs, are used in high level synthesis as quality measures. However, these traditional design quality measures may not reflect the real physical design. To establish quality measures based on the physical designs, we propose layout estimation models for two commonly used data path and control layout architectures. The results show that quality measures deriving from our models give an accurate prediction of the final layout. The results also show that traditional cost functions are not good indicators for optimization in high level synthesis