Fault tolerant on board networks with priorities

International audienceWe consider on-board networks in satellites interconnecting entering signals (inputs) to amplifiers (outputs). The connections are made via expensive switches, each of which has four available links. The paths connecting inputs to outputs should be link-disjoint. Some of the input signals, called priorities, must be connected to the amplifiers which provide the best quality of service (that is to some specific outputs). In practice, amplifiers are prone to fail and the faults cannot be repaired. Therefore, extra outputs have to be built into the network to ensure that every input can be routed to operational outputs. Given three integers, $n$, $p$, and $f$, we would like to design a low cost network (where the network cost is proportional to the total number of switches) such that it is possible to route all $n$ inputs to $n$ operational amplifiers, and to route the $p$ priorities to the $p$ best quality amplifiers for any set of $f$ faulty and $p$ best-quality amplifiers. Let $R(n,p,f)$ be the minimum number of switches of such a network. We prove here that $R(n,p,f)\leq \frac{n+f}{2} \lceil \log_2 p \rceil +\frac{5}{2}(n-p) +g(f)$ with $g$ a function depending only on $f$. We then compute $R(n,p,f)$ exactly for a few small values of $p$ and $f$

Fault tolerant on-board networks with priorities

We consider on-board networks in satellites interconnecting entering signals (inputs) to amplifiers (outputs). The connections are made via expensive switches with four links available. The paths connecting inputs to outputs should be link-disjoint. Some of the input signals, called priorities, must be connected to the amplifiers which provide the best quality of service (that is to some specific outputs). In practice, amplifiers are prone to fail and the faults cannot be repaired. Therefore, extra outputs have to be built into the network to ensure that every input can be routed to operational outputs. Given three integers, $n$, $p$, and $f$, we would like to design a low cost network (where the network cost is proportional to the total number of switches) such that it is possible to route all $n$ inputs to $n$ operational amplifiers and to route the $p$ priorities to the $p$ best quality amplifiers for any set of $f$ faulty and $p$ best-quality amplifiers. Let $R(n,p,f)$ be the minimum number of switches of such a network. We prove here that R(n,p,f)\leq\fracn+f2 \lceil\log_2 p \rceil+\frac52(n-p) +g(f) with $g$ a function depending only on $f$. We then give exact values of $R(n,p,f)$ for small $p$ and $f$

Design of fault tolerant on board networks with priorities via selectors

We consider on-board networks in satellites interconnecting entering signals (inputs) to amplifiers (outputs). The connections are made via expensive switches with four links available. The paths connecting inputs to outputs should be link-disjoint. Among the input signals, some of them, called priorities, must be connected to the amplifiers which provide the best quality of service (that is to some specific outputs). In practice, amplifiers are subject to faults that cannot be repaired. Therefore we need to add extra outputs to ensure the existence of sufficiently many valid ones. Given n inputs, p priorities and k faults, the problem consists in designing a low cost network (i. e. with the minimum number of switches) where it is possible to route the p priorities to the p best quality amplifiers and the other inputs to some valid amplifiers, for any sets of k faulty and p best quality amplifiers. Let N(n,p,k) be the minimum number of switches of a such a network, called repartitor. Bermond, Havet and Toth proved that N(n,p,0)< n-p + n/2 log p and some exact values of N(n, p, k) were given when p and k are small. A (n,0, k)-repartitor is called a (n, n+k)-selector and the minimum number of switches of a (p, n)-selector is denoted by S(p, n). A selector is intrinsically easier to design than general repartitors since there exists only one type of signals to route instead of two. The approach of this paper is to construct (n, p, k)-repartitors from selectors. We show that N(n, p, k) < S( p, p+k) + S(n+k, p+k) + S(n-p, p+k) + n + k. Then we prove that S(p, n) < 33 n + 4 p + O(log n) which implies N( n, p, k)< 71 n + 37 p + 108 k + O(log ( n+ k)). At last, we exhibit minimum (p, n)-selectors when p is at most 6

On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices

Unattended network operations technology assessment study. Technical support for defining advanced satellite systems concepts

The results are summarized of an unattended network operations technology assessment study for the Space Exploration Initiative (SEI). The scope of the work included: (1) identified possible enhancements due to the proposed Mars communications network; (2) identified network operations on Mars; (3) performed a technology assessment of possible supporting technologies based on current and future approaches to network operations; and (4) developed a plan for the testing and development of these technologies. The most important results obtained are as follows: (1) addition of a third Mars Relay Satellite (MRS) and MRS cross link capabilities will enhance the network's fault tolerance capabilities through improved connectivity; (2) network functions can be divided into the six basic ISO network functional groups; (3) distributed artificial intelligence technologies will augment more traditional network management technologies to form the technological infrastructure of a virtually unattended network; and (4) a great effort is required to bring the current network technology levels for manned space communications up to the level needed for an automated fault tolerance Mars communications network

Distributed control of a fault tolerant modular multilevel inverter for direct-drive wind turbine grid interfacing

Modular generator and converter topologies are being pursued for large offshore wind turbines to achieve fault tolerance and high reliability. A centralized controller presents a single critical point of failure which has prevented a truly modular and fault tolerant system from being obtained. This study analyses the inverter circuit control requirements during normal operation and grid fault ride-through, and proposes a distributed controller design to allow inverter modules to operate independently of each other. All the modules independently estimate the grid voltage magnitude and position, and the modules are synchronised together over a CAN bus. The CAN bus is also used to interleave the PWM switching of the modules and synchronise the ADC sampling. The controller structure and algorithms are tested by laboratory experiments with respect to normal operation, initial synchronization to the grid, module fault tolerance and grid fault ride-through

Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 1: Army fault tolerant architecture overview

Digital computing systems needed for Army programs such as the Computer-Aided Low Altitude Helicopter Flight Program and the Armored Systems Modernization (ASM) vehicles may be characterized by high computational throughput and input/output bandwidth, hard real-time response, high reliability and availability, and maintainability, testability, and producibility requirements. In addition, such a system should be affordable to produce, procure, maintain, and upgrade. To address these needs, the Army Fault Tolerant Architecture (AFTA) is being designed and constructed under a three-year program comprised of a conceptual study, detailed design and fabrication, and demonstration and validation phases. Described here are the results of the conceptual study phase of the AFTA development. Given here is an introduction to the AFTA program, its objectives, and key elements of its technical approach. A format is designed for representing mission requirements in a manner suitable for first order AFTA sizing and analysis, followed by a discussion of the current state of mission requirements acquisition for the targeted Army missions. An overview is given of AFTA's architectural theory of operation

NASA. Lewis Research Center Advanced Modulation and Coding Project: Introduction and overview

The Advanced Modulation and Coding Project at LeRC is sponsored by the Office of Space Science and Applications, Communications Division, Code EC, at NASA Headquarters and conducted by the Digital Systems Technology Branch of the Space Electronics Division. Advanced Modulation and Coding is one of three focused technology development projects within the branch's overall Processing and Switching Program. The program consists of industry contracts for developing proof-of-concept (POC) and demonstration model hardware, university grants for analyzing advanced techniques, and in-house integration and testing of performance verification and systems evaluation. The Advanced Modulation and Coding Project is broken into five elements: (1) bandwidth- and power-efficient modems; (2) high-speed codecs; (3) digital modems; (4) multichannel demodulators; and (5) very high-data-rate modems. At least one contract and one grant were awarded for each element

Assessment team report on flight-critical systems research at NASA Langley Research Center

The quality, coverage, and distribution of effort of the flight-critical systems research program at NASA Langley Research Center was assessed. Within the scope of the Assessment Team's review, the research program was found to be very sound. All tasks under the current research program were at least partially addressing the industry needs. General recommendations made were to expand the program resources to provide additional coverage of high priority industry needs, including operations and maintenance, and to focus the program on an actual hardware and software system that is under development