Real Time Fault Detection and Diagnostics Using FPGA-Based Architecture

Errors within circuits caused by radiation continue to be an important concern to developers. A new methodology of real time fault detection and diagnostics utilizing FPGA based architectures while under radiation were investigated in this research. The contributions of this research are focused on three areas; a full test platform to evaluate a circuit while under irradiation, an algorithm to detect and diagnose fault locations within a circuit, and finally to characterize Triple Design Triple Modular Redundancy (TDTMR), a new form of TMR. Five different test setups, injected fault test, gamma radiation test, thermal radiation test, optical laser test, and optical flash test, were used to assess the effectiveness of these three research goals. The testing platform was constructed with two FPGA boards, the Device Under Test (DUT) and the controller board, to generate and evaluate specific vector sets sent to the DUT. The testing platform combines a myriad of testing and measuring equipment and work hours onto one small reprogrammable and reusable FPGA. This device was able to be used in multiple test setups. The controlling logic can be interchanged to test multiple circuit designs under various forms of radiation. The detection and diagnostic algorithm was designed to determine fault locations in real time. The algorithm used for diagnosing the fault location uses inverse deductive elimination. By using test generation tools, fault lists were developed. The fault lists were used to narrow \ the possible fault locations within the circuit. The algorithm is able to detect single stuck at faults based on these lists. The algorithm can also detect multiple output errors but not able to diagnose multiple stuck at faults in real time

The Telecommunications and Data Acquisition Report

Deep Space Network advanced systems, very large scale integration architecture for decoders, radar interface and control units, microwave time delays, microwave antenna holography, and a radio frequency interference survey are among the topics discussed

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

The Logic of Random Pulses: Stochastic Computing.

Recent developments in the field of electronics have produced nano-scale devices whose operation can only be described in probabilistic terms. In contrast with the conventional deterministic computing that has dominated the digital world for decades, we investigate a fundamentally different technique that is probabilistic by nature, namely, stochastic computing (SC). In SC, numbers are represented by bit-streams of 0's and 1's, in which the probability of seeing a 1 denotes the value of the number. The main benefit of SC is that complicated arithmetic computation can be performed by simple logic circuits. For example, a single (logic) AND gate performs multiplication. The dissertation begins with a comprehensive survey of SC and its applications. We highlight its main challenges, which include long computation time and low accuracy, as well as the lack of general design methods. We then address some of the more important challenges. We introduce a new SC design method, called STRAUSS, that generates efficient SC circuits for arbitrary target functions. We then address the problems arising from correlation among stochastic numbers (SNs). In particular, we show that, contrary to general belief, correlation can sometimes serve as a resource in SC design. We also show that unlike conventional circuits, SC circuits can tolerate high error rates and are hence useful in some new applications that involve nondeterministic behavior in the underlying circuitry. Finally, we show how SC's properties can be exploited in the design of an efficient vision chip that is suitable for retinal implants. In particular, we show that SC circuits can directly operate on signals with neural encoding, which eliminates the need for data conversion.PhDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113561/1/alaghi_1.pd

Test methodologies of VLSI circuits using scanning electron microscope.

by Chan Lap-kong.Thesis (M.Phil.)--Chinese University of Hong Kong, 1994.Includes bibliographical references (leaves 77-80).ABSTRACTACKNOWLEDGEMENTSLIST OF FIGURESChapter 1. --- INTRODUCTION --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Problems in Testing VLSI Circuits --- p.3Chapter 1.2.1 --- Test-cost-per-gate --- p.3Chapter 1.2.2 --- Tester Complexity --- p.3Chapter 1.3 --- Tester Based on Terminals Characteristics -Automatic Testing Equipment(ATE) --- p.4Chapter 1.4 --- Tester Based on Terminal and Internal Characteristics --- p.6Chapter 1.4.1 --- Mechanical Probing Method --- p.6Chapter 1.4.2 --- E-beam Probing Method --- p.7Chapter 1.5 --- Movitation for this Research --- p.7Chapter 1.6 --- Outline of the Remaining Chapters --- p.9Chapter 2. --- E-BEAM TESTER --- p.10Chapter 2.1 --- State-of-art of E-Beam Tester --- p.10Chapter 2.2 --- An Electron-optical Column of a SEM --- p.12Chapter 2.3 --- Beam Rastering Methods --- p.13Chapter 2.4 --- Voltage Contrast Phenomenon --- p.14Chapter 2.5 --- Configuration of an E-Beam Test System --- p.18Chapter 2.6 --- Advantages of an E-beam Tester --- p.20Chapter 3. --- BASIC PRINCIPLES --- p.21Chapter 3.1 --- Single-Stuck-At Fault Model --- p.21Chapter 3.2 --- Observability and Controllability --- p.24Chapter 3.3 --- Netlist Format --- p.25Chapter 3.4 --- Level --- p.27Chapter 3.5 --- Reconvergent Fanout --- p.28Chapter 4. --- CONVENTIONAL TEST GENERATION --- p.29Chapter 4.1 --- Conventional Automatic Test Generation for ATEs --- p.29Chapter 4.3 --- Conventional E-Beam Test Generation --- p.31Chapter 5. --- TEST AND PROBE POINT GENERATION --- p.32Chapter 5.1 --- Wafer Stage E-beam Testing --- p.32Chapter 5.2 --- Critical Paths Generation --- p.33Chapter 5.3 --- Assumptions of the Test and Probe Point Generation Algorithm --- p.35Chapter 5.4 --- Rules of the Test and Probe Point Generation Algorithm --- p.36Chapter 5.5 --- Probe Points Selection and Reduction --- p.38Chapter 5.6 --- Test and Probe Point Generation Algorithm --- p.40Chapter 5.7 --- Propagation and Justification at Fanout Site --- p.42Chapter 6. --- EXAMPLES --- p.45Chapter 6.1 --- Example of Test and Probe Point Generation for Circuit sc2 --- p.45Chapter 6.2 --- Example of Test and Probe Point Generation for Circuit sfc4 --- p.53Chapter 7. --- CONCLUSIONS --- p.61Chapter 7.1 --- Summary of Results --- p.61Chapter 7.2 --- Further Research --- p.63APPENDIXAppendix A: Algorithm to Find Reconvergent FanoutsAppendix B: Results of Test Generation for Circuit sc1Appendix C: Results of Test Generation for Circuit sc3REFERENCES --- p.7

Low-Power and Error-Resilient VLSI Circuits and Systems.

Efficient low-power operation is critically important for the success of the next-generation signal processing applications. Device and supply voltage have been continuously scaled to meet a more constrained power envelope, but scaling has created resiliency challenges, including increasing timing faults and soft errors. Our research aims at designing low-power and robust circuits and systems for signal processing by drawing circuit, architecture, and algorithm approaches. To gain an insight into the system faults due to supply voltage reduction, we researched the two primary effects that determine the minimum supply voltage (VMIN) in Intel’s tri-gate CMOS technology, namely process variations and gate-dielectric soft breakdown. We determined that voltage scaling increases the timing window that sequential circuits are vulnerable. Thus, we proposed a new hold-time violation metric to define hold-time VMIN, which has been adopted as a new design standard. Device scaling increases soft errors which affect circuit reliability. Through extensive soft error characterization using two 65nm CMOS test chips, we studied the soft error mechanisms and its dependence on supply voltage and clock frequency. This study laid the foundation of the first 65nm DSP chip design for a NASA spaceflight project. To mitigate such random errors, we proposed a new confidence-driven architecture that effectively enhances the error resiliency of deeply scaled CMOS and post-CMOS circuits. Designing low-power resilient systems can effectively leverage application-specific algorithmic approaches. To explore design opportunities in the algorithmic domain, we demonstrate an application-specific detection and decoding processor for multiple-input multiple-output (MIMO) wireless communication. To enhance the receive error rate for a robust wireless communication, we designed a joint detection and decoding technique by enclosing detection and decoding in an iterative loop to enhance both interference cancellation and error reduction. A proof-of-concept chip design was fabricated for the next-generation 4x4 256QAM MIMO systems. Through algorithm-architecture optimizations and low-power circuit techniques, our design achieves significant improvements in throughput, energy efficiency and error rate, paving the way for future developments in this area.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/110323/1/uchchen_1.pd

Application of advanced technology to space automation

Automated operations in space provide the key to optimized mission design and data acquisition at minimum cost for the future. The results of this study strongly accentuate this statement and should provide further incentive for immediate development of specific automtion technology as defined herein. Essential automation technology requirements were identified for future programs. The study was undertaken to address the future role of automation in the space program, the potential benefits to be derived, and the technology efforts that should be directed toward obtaining these benefits