An Efficiency Study on Fault Tolerent Fir Filters

In this Digital World, Digital filters are the boom for modern digital communications in which Fir filters play a vital role. But the reliability of these filters is still a paradox. Nowadays electronic devices with multiple numbers of filters are used in various fields. Hence the performance and reliability of the filters must be improved. A number of techniques have been introduced to detect and correct errors that occur in those filter circuits. In this paper, the use of hamming code error correction technique on 4 tap fir filters are studied in order to obtain optimized and efficient reliability

AN ERROR PRONE DIGITAL FILTERS BY APPLYING CODING FORMULATIONS

Within this ECC-based plan, the coding from the redundant filters is dependent on simple additions that switch the XOR binary operations in traditional ECCs. However, since both inputs and outputs from the filters are sequences of figures, a far more general coding may be used. Particularly, soft errors are an essential issue, and lots of techniques happen to be suggested through the years to mitigate them. The security of parallel filters only has been lately considered. This brief studies the security of parallel filters using more general coding techniques. Particularly, a vital difference with ECCs is the fact that both filter inputs and outputs are figures. To identify and proper errors, each filter may very well be a little within an ECC, and redundant filters can be included to form parity check bits. This differs from the approach suggested within this brief, where inputs are encoded however the processing from the filters isn't modified. ECC-based plan cuts down on the protection overhead compared by using TMR. The input signals are encoded utilizing a matrix with arbitrary coefficients to create the signals that go into the four original and 2 redundant filters. To simplify the implementation, individual’s rows must have values that minimize the complexness of multiplications and the rise in the dynamic range within the redundant filters. The sensible implementation was highlighted with two situation studies which were evaluated to have an FPGA implementation and in contrast to a formerly suggested technique. That technique depends on using ECCs so that each filter is treated like a bit within the ECC. The outcomes reveal that the suggested plan outperforms the ECC technique (lower costs achieving similar fault-tolerant capacity). Therefore, the suggested technique could be helpful to apply fault tolerant parallel filters

Improved Fault Tolerance for Parallel FFT

Digital filters are mainly used in signal processing and communication systems. Soft errors are major threats of the modern communication system. Now a day’s complexity of communication and signal processing increases day by day. So reliability of the system is critical and fault tolerance technique is needed. In parallel FFT protection using ECC and parseval check can be used for error detection and correction. In this project is to reduce the entire area of the fault tolerant system by using pipelined method. In pipelined FFT consist of two butterfly structure. Each stage is replaced by a single butterfly structure. Experimental results show that proposed technique reduces the area and delay of the system. This project is mainly focused on the area of the system. Proposed technique is more efficient and reduces the complexity of the entire system