Fault Modeling of Graphene Nanoribbon FET Logic Circuits

[EN] Due to the increasing defect rates in highly scaled complementary metal-oxide-semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.This work was supported in part by the Spanish Government under the research project TIN2016-81075-R and by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), under the project 200190032.Gil Tomás, DA.; Gracia-Morán, J.; Saiz-Adalid, L.; Gil, P. (2019). Fault Modeling of Graphene Nanoribbon FET Logic Circuits. Electronics. 8(8):1-18. https://doi.org/10.3390/electronics8080851S11888International Technology Roadmap for Semiconductors (ITRS) 2013http://www.itrs2.net/2013-itrs.htmlSchuegraf, K., Abraham, M. C., Brand, A., Naik, M., & Thakur, R. (2013). Semiconductor Logic Technology Innovation to Achieve Sub-10 nm Manufacturing. IEEE Journal of the Electron Devices Society, 1(3), 66-75. doi:10.1109/jeds.2013.2271582International Technology Roadmap for Semiconductors (ITRS) 2015https://bit.ly/2xiiT8PNovoselov, K. S. (2004). Electric Field Effect in Atomically Thin Carbon Films. Science, 306(5696), 666-669. doi:10.1126/science.1102896Geim, A. K., & Novoselov, K. S. (2007). The rise of graphene. Nature Materials, 6(3), 183-191. doi:10.1038/nmat1849Wu, Y., Farmer, D. B., Xia, F., & Avouris, P. (2013). Graphene Electronics: Materials, Devices, and Circuits. Proceedings of the IEEE, 101(7), 1620-1637. doi:10.1109/jproc.2013.2260311Choudhury, M. R., Youngki Yoon, Jing Guo, & Mohanram, K. (2011). Graphene Nanoribbon FETs: Technology Exploration for Performance and Reliability. IEEE Transactions on Nanotechnology, 10(4), 727-736. doi:10.1109/tnano.2010.2073718Avouris, P. (2010). Graphene: Electronic and Photonic Properties and Devices. Nano Letters, 10(11), 4285-4294. doi:10.1021/nl102824hBanadaki, Y. M., & Srivastava, A. (2015). Scaling Effects on Static Metrics and Switching Attributes of Graphene Nanoribbon FET for Emerging Technology. IEEE Transactions on Emerging Topics in Computing, 3(4), 458-469. doi:10.1109/tetc.2015.2445104Avouris, P., Chen, Z., & Perebeinos, V. (2007). Carbon-based electronics. Nature Nanotechnology, 2(10), 605-615. doi:10.1038/nnano.2007.300Banerjee, S. K., Register, L. F., Tutuc, E., Basu, D., Kim, S., Reddy, D., & MacDonald, A. H. (2010). Graphene for CMOS and Beyond CMOS Applications. Proceedings of the IEEE, 98(12), 2032-2046. doi:10.1109/jproc.2010.2064151Schwierz, F. (2013). Graphene Transistors: Status, Prospects, and Problems. Proceedings of the IEEE, 101(7), 1567-1584. doi:10.1109/jproc.2013.2257633Fregonese, S., Magallo, M., Maneux, C., Happy, H., & Zimmer, T. (2013). Scalable Electrical Compact Modeling for Graphene FET Transistors. IEEE Transactions on Nanotechnology, 12(4), 539-546. doi:10.1109/tnano.2013.2257832Chen, Y.-Y., Sangai, A., Rogachev, A., Gholipour, M., Iannaccone, G., Fiori, G., & Chen, D. (2015). A SPICE-Compatible Model of MOS-Type Graphene Nano-Ribbon Field-Effect Transistors Enabling Gate- and Circuit-Level Delay and Power Analysis Under Process Variation. IEEE Transactions on Nanotechnology, 14(6), 1068-1082. doi:10.1109/tnano.2015.2469647Ferrari, A. C., Bonaccorso, F., Fal’ko, V., Novoselov, K. S., Roche, S., Bøggild, P., … Pugno, N. (2015). Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems. Nanoscale, 7(11), 4598-4810. doi:10.1039/c4nr01600aHong, A. J., Song, E. B., Yu, H. S., Allen, M. J., Kim, J., Fowler, J. D., … Wang, K. L. (2011). Graphene Flash Memory. ACS Nano, 5(10), 7812-7817. doi:10.1021/nn201809kJeng, S.-L., Lu, J.-C., & Wang, K. (2007). A Review of Reliability Research on Nanotechnology. IEEE Transactions on Reliability, 56(3), 401-410. doi:10.1109/tr.2007.903188Srinivasu, B., & Sridharan, K. (2017). A Transistor-Level Probabilistic Approach for Reliability Analysis of Arithmetic Circuits With Applications to Emerging Technologies. IEEE Transactions on Reliability, 66(2), 440-457. doi:10.1109/tr.2016.2642168Teixeira Franco, D., Naviner, J.-F., & Naviner, L. (2006). Yield and reliability issues in nanoelectronic technologies. annals of telecommunications - annales des télécommunications, 61(11-12), 1422-1457. doi:10.1007/bf03219903Lin, Y.-M., Jenkins, K. A., Valdes-Garcia, A., Small, J. P., Farmer, D. B., & Avouris, P. (2009). Operation of Graphene Transistors at Gigahertz Frequencies. Nano Letters, 9(1), 422-426. doi:10.1021/nl803316hLiao, L., Lin, Y.-C., Bao, M., Cheng, R., Bai, J., Liu, Y., … Duan, X. (2010). High-speed graphene transistors with a self-aligned nanowire gate. Nature, 467(7313), 305-308. doi:10.1038/nature09405Wang, X., Tabakman, S. M., & Dai, H. (2008). Atomic Layer Deposition of Metal Oxides on Pristine and Functionalized Graphene. Journal of the American Chemical Society, 130(26), 8152-8153. doi:10.1021/ja8023059Geim, A. K. (2009). Graphene: Status and Prospects. Science, 324(5934), 1530-1534. doi:10.1126/science.1158877Mistewicz, K., Nowak, M., Wrzalik, R., Śleziona, J., Wieczorek, J., & Guiseppi-Elie, A. (2016). Ultrasonic processing of SbSI nanowires for their application to gas sensors. Ultrasonics, 69, 67-73. doi:10.1016/j.ultras.2016.04.004Jesionek, M., Nowak, M., Mistewicz, K., Kępińska, M., Stróż, D., Bednarczyk, I., & Paszkiewicz, R. (2018). Sonochemical growth of nanomaterials in carbon nanotube. Ultrasonics, 83, 179-187. doi:10.1016/j.ultras.2017.03.014Chen, X., Seo, D. H., Seo, S., Chung, H., & Wong, H.-S. P. (2012). Graphene Interconnect Lifetime: A Reliability Analysis. IEEE Electron Device Letters, 33(11), 1604-1606. doi:10.1109/led.2012.2211564Wang, Z. F., Zheng, H., Shi, Q. W., & Chen, J. (2009). Emerging nanodevice paradigm. ACM Journal on Emerging Technologies in Computing Systems, 5(1), 1-19. doi:10.1145/1482613.1482616Dong, J., Xiang, G., Xiang-Yang, K., & Jia-Ming, L. (2007). Atomistic Failure Mechanism of Single Wall Carbon Nanotubes with Small Diameters. Chinese Physics Letters, 24(1), 165-168. doi:10.1088/0256-307x/24/1/045Bu, H., Chen, Y., Zou, M., Yi, H., Bi, K., & Ni, Z. (2009). Atomistic simulations of mechanical properties of graphene nanoribbons. Physics Letters A, 373(37), 3359-3362. doi:10.1016/j.physleta.2009.07.04

Redundant Logic Insertion and Fault Tolerance Improvement in Combinational Circuits

This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In this context, it is discussed how to estimate the fault masking capability of a combinational circuit using the truth-cum-fault enumeration table, and then it is shown how to identify the logic that can introduced to add redundancy into the original circuit without affecting its native functionality and with the aim of improving its fault tolerance though this would involve some trade-off in the design metrics. However, care should be taken while introducing redundant logic since redundant logic insertion may give rise to new internal nodes and faults on those may impact the fault tolerance of the resulting circuit. The combinational circuit that is considered and its redundant counterparts are all implemented in semi-custom design style using a 32/28nm CMOS digital cell library and their respective design metrics and fault tolerances are compared

RON-BEAM DEBUG AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS

A current research project at IMAG/TIM3 Laboratory aims at an integrated test system combining the use of the Scanning Electron Microscope (SEM), used in voltage contrast mode, with a new high-level approach of fault location in complex VLSI circuits, in order to reach a complete automated diagnosis process. Two research themes are induced by this project, which are: prototype validation of known circuits, on which CAD information is available, and failure analysis of unknown circuits, which are compared to reference circuits. For prototype validation, a knowledge-based approach to fault location is used. Concerning failure analysis, automatic image comparison based on pattern recog- nition techniques is performed. The purpose of the paper is to present these two methodologies, focusing on the SEM-based data acquisition process

Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults

In the relatively young field of fault-tolerant cryptography, the main research effort has focused exclusively on the protection of the data path of cryptographic circuits. To date, however, we have not found any work that aims at protecting the control logic of these circuits against fault attacks, which thus remains the proverbial Achilles’ heel. Motivated by a hypothetical yet realistic fault analysis attack that, in principle, could be mounted against any modular exponentiation engine, even one with appropriate data path protection, we set out to close this remaining gap. In this paper, we present guidelines for the design of multifault-resilient sequential control logic based on standard Error-Detecting Codes (EDCs) with large minimum distance. We introduce a metric that measures the effectiveness of the error detection technique in terms of the effort the attacker has to make in relation to the area overhead spent in implementing the EDC. Our comparison shows that the proposed EDC-based technique provides superior performance when compared against regular N-modular redundancy techniques. Furthermore, our technique scales well and does not affect the critical path delay

A novel genetic algorithm for evolvable hardware

Evolutionary algorithms are used for solving search and optimization problems. A new field in which they are also applied is evolvable hardware, which refers to a self-configurable electronic system. However, evolvable hardware is not widely recognized as a tool for solving real-world applications, because of the scalability problem, which limits the size of the system that may be evolved. In this paper a new genetic algorithm, particularly designed for evolving logic circuits, is presented and tested for its scalability. The proposed algorithm designs and optimizes logic circuits based on a Programmable Logic Array (PLA) structure. Furthermore it allows the evolution of large logic circuits, without the use of any decomposition techniques. The experimental results, based on the evolution of several logic circuits taken from three different benchmarks, prove that the proposed algorithm is very fast, as only a few generations are required to fully evolve the logic circuits. In addition it optimizes the evolved circuits better than the optimization offered by other evolutionary algorithms based on a PLA and FPGA structures

Fault-tolerant sub-lithographic design with rollback recovery

Shrinking feature sizes and energy levels coupled with high clock rates and decreasing node capacitance lead us into a regime where transient errors in logic cannot be ignored. Consequently, several recent studies have focused on feed-forward spatial redundancy techniques to combat these high transient fault rates. To complement these studies, we analyze fine-grained rollback techniques and show that they can offer lower spatial redundancy factors with no significant impact on system performance for fault rates up to one fault per device per ten million cycles of operation (Pf = 10^-7) in systems with 10^12 susceptible devices. Further, we concretely demonstrate these claims on nanowire-based programmable logic arrays. Despite expensive rollback buffers and general-purpose, conservative analysis, we show the area overhead factor of our technique is roughly an order of magnitude lower than a gate level feed-forward redundancy scheme

High quality testing of grid style power gating

This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% test-application-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test qualit