Adaptive motion estimation algorithm and hardware designs for H.264 multiview video coding

Multiview Video Coding (MVC) is the process of efficiently compressing stereo (2 views) or multiview video signals. The improved compression efficiency achieved by H.264 MVC comes with a significant increase in computational complexity. Therefore, in this thesis, we propose novel techniques for significantly reducing the amount of computations performed by full search motion estimation algorithm for H.264 MVC, and therefore significantly reducing the energy consumption of full search motion estimation hardware for H.264 MVC with very small PSNR loss and bitrate increase. We also propose an adaptive fast motion estimation algorithm for reducing the amount of computations performed by H.264 MVC motion estimation, and therefore reducing the energy consumption of H.264 MVC motion estimation hardware even more with additional very small PSNR loss and bitrate increase. We also propose an adaptive H.264 MVC motion estimation hardware for implementing the proposed adaptive fast motion estimation algorithm. The proposed motion estimation hardware is implemented in Verilog HDL and mapped to a Xilinx Virtex-6 FPGA. The proposed motion estimation hardware has less energy consumption than the full search motion estimation hardware for H.264 MVC and the full search motion estimation hardware for H.264 MVC including the proposed computation reduction techniques

Fast adaptive motion estimation for H.264

H.264 motion estimation achieves better compression efficiency of video coding than previous video standards (e.g. MPEG-2, H.263, and JPEG). But it leads to higher computational cost and complexity in coding. In this study we propose an efficient early termination searching method to reduce the computational complexity and achieve better compression ratio. Adaptive search strategy is applied to reduce the search point in a search range. Furthermore this study presents an analysis of the performance of the proposed algorithm in terms of motion estimation time, total encoding time, and video quality (PSNR). Simulation result shows that compared to Full Search (FS), this algorithm achieves up to 60% reduction in motion estimation time without degrading the video quality

Low energy motion estimation hardware designs for h.264 multiview video coding

Multiview Video Coding (MVC) is the process of efficiently compressing stereo (2 views) or multiview video signals. The improved compression efficiency achieved by H.264 MVC comes with a significant increase in computational complexity. Temporal prediction and inter-view prediction are the most computationally intensive parts of H.264 MVC. Therefore, in this thesis, we propose an H.264 MVC full search motion estimation hardware for implementing the temporal and inter-view predictions including several novel energy reduction techniques. The proposed motion estimation hardware is implemented in Verilog HDL and mapped to a Xilinx Virtex-6 FPGA. The FPGA implementation is capable of processing 60 frames per second of VGA size stereo view video sequence. It consumes 65% less energy than H.264 MVC full search motion estimation hardware not including the novel energy reduction techniques with very small PSNR loss and bitrate increase. We also propose a vector prediction based fast motion estimation algorithm for reducing the energy consumption of H.264 MVC motion estimation hardware with additional very small PSNR loss and bitrate increase. We also propose an H.264 MVC motion estimation hardware for implementing the proposed fast motion estimation algorithm. The proposed motion estimation hardware is implemented in Verilog HDL and mapped to a Xilinx Virtex-6 FPGA. The FPGA implementation is capable of processing 92 frames per second of VGA size three view video sequence. It consumes 91% less energy than H.264 MVC full search motion estimation hardware not including the novel energy reduction techniques with very small PSNR loss and bitrate increase

Mode decision for the H.264/AVC video coding standard

H.264/AVC video coding standard gives us a very promising future for the field of video broadcasting and communication because of its high coding efficiency compared with other older video coding standards. However, high coding efficiency also carries high computational complexity. Fast motion estimation and fast mode decision are two very useful techniques which can significantly reduce computational complexity. This thesis focuses on the field of fast mode decision. The goal of this thesis is that for very similar RD performance compared with H.264/AVC video coding standard, we aim to find new fast mode decision techniques which can afford significant time savings. [Continues.

Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation using Graphics Processing Unit and Dedicated Hardware

Heterogeneous systems on a single chip composed of CPU, Graphical Processing Unit (GPU), and Field Programmable Gate Array (FPGA) are expected to emerge in near future. In this context, the System on Chip (SoC) can be dynamically adapted to employ different architectures for execution of data-intensive applications. Motion estimation is one such task that can be accelerated using FPGA and GPU for high performance H.264/AVC encoder implementation. In most of works on parallel implementation of motion estimation, the bit rate cost of motion vectors is generally ignored. On the contrary, this paper presents a fast rate-distortion optimized parallel motion estimation algorithm implemented on GPU using OpenCL and FPGA/ASIC using VHDL. The predicted motion vectors are estimated from temporally preceding motion vectors and used for evaluating the bit rate cost of the motion vectors simultaneously. The experimental results show that the proposed scheme achieves significant speedup on GPU and FPGA, and has comparable ratedistortion performance with respect to sequential fast motion estimation algorithm

A Survey on Block Matching Algorithms for Video Coding

Block matching algorithm (BMA) for motion estimation (ME) is the heart to many motion-compensated video-coding techniques/standards, such as ISO MPEG-1/2/4 and ITU-T H.261/262/263/264/265, to reduce the temporal redundancy between different frames. During the last three decades, hundreds of fast block matching algorithms have been proposed. The shape and size of search patterns in motion estimation will influence more on the searching speed and quality of performance. This article provides an overview of the famous block matching algorithms and compares their computational complexity and motion prediction quality

A New Fast Motion Estimation and Mode Decision algorithm for H.264 Depth Maps encoding in Free Viewpoint TV

In this paper, we consider a scenario where 3D scenes are modeled through a View+Depth representation. This representation is to be used at the rendering side to generate synthetic views for free viewpoint video. The encoding of both type of data (view and depth) is carried out using two H.264/AVC encoders. In this scenario we address the reduction of the encoding complexity of depth data. Firstly, an analysis of the Mode Decision and Motion Estimation processes has been conducted for both view and depth sequences, in order to capture the correlation between them. Taking advantage of this correlation, we propose a fast mode decision and motion estimation algorithm for the depth encoding. Results show that the proposed algorithm reduces the computational burden with a negligible loss in terms of quality of the rendered synthetic views. Quality measurements have been conducted using the Video Quality Metric

H.264 motion estimator design

Recently, a new international standard for video compression named H.264 / MPEG-4 Part 10 is developed. This new standard offers significantly better video compression efficiency than previous international standards. The variable block size motion estimation is the most compute-intensive part of an H.264 video encoder. The full search method is impractical for real-time implementations since it requires a high computational complexity. Therefore, many fast motion estimation algorithms have been developed for real-time implementations. In this thesis, we used an SAD reuse based hierarchical motion estimation algorithm for real-time H.264 / MPEG-4 Part 10 video coding. This algorithm uses the Lagrangian cost parameter (SAD+λR) for selecting the best motion vector. We designed a high performance and low cost hardware architecture for real-time implementation of this algorithm. We have considered several alternative designs and decided on this architecture based on a cost/performance analysis. This architecture uses a novel data flow resulting in a low cost and high performance hardware. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 63 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 25 VGA frames (640x480) or 76 CIF frames (352x288) per second