COMPUTER-AIDED LAYOUT INTERCONNECTION EXTRACTION OF CELL-STRUCTURED INTEGRATED CIRCUIT MASKS

The program CELLINEX presented in the paper finds the cellular interconnections from the layout of cell-structured integrated circuits. From this the logical description of the circuit is generated and it is checked whether the realized interconnections are permitted or not and whether there are trivial lacks or not. The paper describes the characteristics of the program and the most important algorithms. Some kinds of documentation of the results are presented

Design Integrity and Immunity Checking: A New Look at Layout Verification and Design Rule Checking

A program implementing a novel approach to layout verification is presented. The approach uses topological and device information to eliminate most false and unchecked errors. This technique, coupled with a hierarchical front end to eliminated redundant checks, is appropriate for layout verification of VLSI designs. Design rules appropriate for this technique, some usage rules in the context of structured design, and a discussion of the future of design rule checking are also presented

Using topological sweep to extract the boundaries of regions in maps represented by region quadtrees

A variant of the plane sweep paradigm known as topological sweep is adapted to solve geometric problems involving two-dimensional regions when the underlying representation is a region quadtree. The utility of this technique is illustrated by showing how it can be used to extract the boundaries of a map in O(M) space and O(Ma(M)) time, where M is the number of quad tree blocks in the map, and a(·) is the (extremely slowly growing) inverse of Ackerman's function. The algorithm works for maps that contain multiple regions as well as holes. The algorithm makes use of active objects (in the form of regions) and an active border. It keeps track of the current position in the active border so that at each step no search is necessary. The algorithm represents a considerable improvement over a previous approach whose worst-case execution time is proportional to the product of the number of blocks in the map and the resolution of the quad tree (i.e., the maximum level of decomposition). The algorithm works for many different quadtree representations including those where the quadtree is stored in external storage

Step into Computational Geometry Notebook III

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryJoint Services Electronics Program / N00014-79-C-0424National Science FoundationControl Data Corporatio

Implementation of a design rule checker for silicon wafer fabrication

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (leaves 90-92).by Evren R. Ünver.M.Eng

Computer aids for the design of large scale integrated circuits.

The work described in this thesis is concerned with the development of CADIC (Computer Aided Design of Integrated Circuits), a suite of computer programs which allows the user to design integrated circuit layouts at the geometric level. Initially, a review of existing computer aids to integrated circuit design is carried out. Advantages and disadvantages of each computer aid is discused, and the approach taken by CADIC justified in the light of the review. The hardware associated with a design aid can greatly influence its performance and useability. For this reason, a critical review of available graphic terminals is also undertaken. The requirements, logistics, and operation of CADIC is then discussed in detail. CADIC provides a consise range of features to aid in the design and testing of integrated circuit layouts. The most important features are however CADIC's high efficiency in processing layout data, and the implementation of complete on-line design rule checking. Utilization of these features allows CADIC to substantially reduce the lengthy design turnaround time normally associated with manual design aids. Finally, the performance of CADIC is presented. Analysis of the results show that CADIC is very efficient at data processing, especially when small sections of the layout are considered. CADIC can also perform complete on-line design rule checking well within the time it takes the designer to start adding the next shape