Failure Analysis of ESD-stressed SiC MESFET

International audienceReliability studies are required for SiC device development. In a previous work we studied the intrinsicESD robustness of a SiC MESFET. The failure mechanism was related to the triggering of an NPN parasitictransistor. In this work, a new MESFET layout is considered, which optionally include a Zener diode for internalprotection. TLP testing and failure analysis has been carried out. Two new failure mechanisms are evidenced.Based on this knowledge, solutions are proposed to further improve the ESD robustness