Jatkuvien menetelmien parantaminen järjestelmäpiiri kehityksessä

This work is about continuous practices in embedded System-on-Chip development. Continuous practices include continuous integration, continuous delivery, and continuous development. These practices mean committing small code changes often to the repository’s main branch. Then the changes are automatically tested and integrated with the rest of the system. In the case of continuous deployment, all the changes are automatically deployed to production without any human interaction. Continuous practices are meant to make development faster and more effective, give feedback faster and improve quality by reducing bugs. These tasks are important in today’s industry which is continuously changing, and customer satisfaction is as important as ever. This creates the demand to deliver new products and updates rapidly along with high quality. In the Nokia Networks’ System-on-Chip department there was a need to increase the level of automated processes by improving the continuous practices. This work studies continuous practices based on literature and identifies ways to improve continuous practice processes used at System-on-Chip development. The implementation of this work was done at the System-on-Chip departments’ software unit where the current state was analysed. The main improvement points found in the analysis were related to automated function, investment and working habits. Based on the analysis the implementation plan was formed. The implementation included adding more functions to the continuous integration server, improving feedback and making the results more visible. These were done by creating more Jenkins jobs and integrating Robot Framework to the testing. All the improvements were not possible to do within the time scope or without the support of the whole department. Therefore, those problem points were analysed, and detailed plans were formed to solve them in the near future

A scalable, portable, FPGA-based implementation of the Unscented Kalman Filter

Sustained technological progress has come to a point where robotic/autonomous systems may well soon become ubiquitous. In order for these systems to actually be useful, an increase in autonomous capability is necessary for aerospace, as well as other, applications. Greater aerospace autonomous capability means there is a need for high performance state estimation. However, the desire to reduce costs through simplified development processes and compact form factors can limit performance. A hardware-based approach, such as using a Field Programmable Gate Array (FPGA), is common when high performance is required, but hardware approaches tend to have a more complicated development process when compared to traditional software approaches; greater development complexity, in turn, results in higher costs. Leveraging the advantages of both hardware-based and software-based approaches, a hardware/software (HW/SW) codesign of the Unscented Kalman Filter (UKF), based on an FPGA, is presented. The UKF is split into an application-specific part, implemented in software to retain portability, and a non-application-specific part, implemented in hardware as a parameterisable IP core to increase performance. The codesign is split into three versions (Serial, Parallel and Pipeline) to provide flexibility when choosing the balance between resources and performance, allowing system designers to simplify the development process. Simulation results demonstrating two possible implementations of the design, a nanosatellite application and a Simultaneous Localisation and Mapping (SLAM) application, are presented. These results validate the performance of the HW/SW UKF and demonstrate its portability, particularly in small aerospace systems. Implementation (synthesis, timing, power) details for a variety of situations are presented and analysed to demonstrate how the HW/SW codesign can be scaled for any application

FPGA-based many-core System-on-Chip design

International audienceMassively parallel architectures are proposed as a promising solution to speed up data-intensive applications and provide the required computational power. In particular, Single Instruction Multiple Data (SIMD) many-core architec-tures have been adopted for multimedia and signal processing applications with massive amounts of data parallelism where both performance and flexible programmability are important metrics. However, this class of processors has faced many challenges due to its increasing fabrication cost and design complexity. Moreover, the increasing gap between design productivity and chip complexity requires new design methods. Nowadays, the recent evolution of silicon integration technology, on the one hand, and the wide usage of reusable Intellectual Property (IP) cores and FPGAs (Field Pro-grammable Gate Arrays), on the other hand, are attractive solutions to meet these challenges and reduce the time-to-market. The objective of this work is to study the performances of massively parallel SIMD on-chip architecture