AN OFDM platform for wireless systems testing: alamouti 2x1 MIMO example

In this paper, we present a real-time implementation of an OFDM hardware platform. The platform is based on HW blocks that can be put together to configure a wireless system based on OFDM modulation. The platform can be easily upgraded to test pre-coding cooperation algorithms. We evaluate the platform to implement a diversity Alamouti 2×1 MIMO scheme wireless system. The testbed is implemented using Field- Programmable Gate Array (FPGAs) through Xilinx System Generator for DSP. Blocks for time-domain synchronization and channel estimation are key components necessary in transmission system that require good time synchronization and channel estimation for efficient demodulation

HARDWARE IMPLEMENTATION OF MISO ON ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING PLATFORM WITH THE HELP OF ALAMOUTI ALGORITHM

Many software based OFDM techniques were proposed from last half decade to improve the performance of the system. This paper tried to implement the same with Hardware implementation. We created Hardware based MISO platform with OFDM. We implemented Alamouti algorithm on this test bed. The test bed is implemented with the help of Field Programmable Gate Array (FPGA). The test bed is functionalized with the help of FPGA through Xilinx based system generator for DSP. In this paper we considered the 2×1 MISO implementation with Alamouti algorithm. The simulation results showed that BER and SNR are considerably high for MISO than SISO. The results also proved that proposed OFDM based Alamouti implementation for MISO is excellent in all performance criterionsMany software based OFDM techniques were proposed from last half decade to improve the performance of the system. This paper tried to implement the same with Hardware implementation. We created Hardware based MISO platform with OFDM. We implemented Alamouti algorithm on this test bed. The test bed is implemented with the help of Field Programmable Gate Array (FPGA). The test bed is functionalized with the help of FPGA through Xilinx based system generator for DSP. In this paper we considered the 2×1 MISO implementation with Alamouti algorithm. The simulation results showed that BER and SNR are considerably high for MISO than SISO. The results also proved that proposed OFDM based Alamouti implementation for MISO is excellent in all performance criterion

System capacity enhancement for 5G network and beyond

A thesis submitted to the University of Bedfordshire, in fulfilment of the requirements for the degree of Doctor of PhilosophyThe demand for wireless digital data is dramatically increasing year over year. Wireless communication systems like Laptops, Smart phones, Tablets, Smart watch, Virtual Reality devices and so on are becoming an important part of people’s daily life. The number of mobile devices is increasing at a very fast speed as well as the requirements for mobile devices such as super high-resolution image/video, fast download speed, very short latency and high reliability, which raise challenges to the existing wireless communication networks. Unlike the previous four generation communication networks, the fifth-generation (5G) wireless communication network includes many technologies such as millimetre-wave communication, massive multiple-input multiple-output (MIMO), visual light communication (VLC), heterogeneous network (HetNet) and so forth. Although 5G has not been standardised yet, these above technologies have been studied in both academia and industry and the goal of the research is to enhance and improve the system capacity for 5G networks and beyond by studying some key problems and providing some effective solutions existing in the above technologies from system implementation and hardware impairments’ perspective. The key problems studied in this thesis include interference cancellation in HetNet, impairments calibration for massive MIMO, channel state estimation for VLC, and low latency parallel Turbo decoding technique. Firstly, inter-cell interference in HetNet is studied and a cell specific reference signal (CRS) interference cancellation method is proposed to mitigate the performance degrade in enhanced inter-cell interference coordination (eICIC). This method takes carrier frequency offset (CFO) and timing offset (TO) of the user’s received signal into account. By reconstructing the interfering signal and cancelling it afterwards, the capacity of HetNet is enhanced. Secondly, for massive MIMO systems, the radio frequency (RF) impairments of the hardware will degrade the beamforming performance. When operated in time duplex division (TDD) mode, a massive MIMO system relies on the reciprocity of the channel which can be broken by the transmitter and receiver RF impairments. Impairments calibration has been studied and a closed-loop reciprocity calibration method is proposed in this thesis. A test device (TD) is introduced in this calibration method that can estimate the transmitters’ impairments over-the-air and feed the results back to the base station via the Internet. The uplink pilots sent by the TD can assist the BS receivers’ impairment estimation. With both the uplink and downlink impairments estimates, the reciprocity calibration coefficients can be obtained. By computer simulation and lab experiment, the performance of the proposed method is evaluated. Channel coding is an essential part of a wireless communication system which helps fight with noise and get correct information delivery. Turbo codes is one of the most reliable codes that has been used in many standards such as WiMAX and LTE. However, the decoding process of turbo codes is time-consuming and the decoding latency should be improved to meet the requirement of the future network. A reverse interleave address generator is proposed that can reduce the decoding time and a low latency parallel turbo decoder has been implemented on a FPGA platform. The simulation and experiment results prove the effectiveness of the address generator and show that there is a trade-off between latency and throughput with a limited hardware resource. Apart from the above contributions, this thesis also investigated multi-user precoding for MIMO VLC systems. As a green and secure technology, VLC is achieving more and more attention and could become a part of 5G network especially for indoor communication. For indoor scenario, the MIMO VLC channel could be easily ill-conditioned. Hence, it is important to study the impact of the channel state to the precoding performance. A channel state estimation method is proposed based on the signal to interference noise ratio (SINR) of the users’ received signal. Simulation results show that it can enhance the capacity of the indoor MIMO VLC system

An FPGA implementation of OFDM transceiver for LTE applications

The paper presents a real-time transceiver using an Orthogonal Frequency-Division Multiplexing (OFDM) signaling scheme. The transceiver is implemented on a Field- Programmable Gate Array (FPGA) through Xilinx System Generator for DSP and includes all the blocks needed for the transmission path of OFDM. The transmitter frame can be reconfigured for different pilot and data schemes. In the receiver, time-domain synchronization is achieved thr ough a joint maximum likelihood (ML) symbol arrival-time and carrier frequency offset (CFO) estimator through the redundant information contained in the cyclic prefix (CP). A least-squares channel estimation retrieves the channel state information and a simple zero-forcing scheme has been implemented for channel equalization. Results show that a rough implementation of the signal path can be impleme nted by using only Xilinx System Generator for DSP

A real-time FPGA-based implementation of a high-performance MIMO-OFDM mobile WiMAX transmitter

The Multiple Input Multiple Output (MIMO)-Orthogonal Frequency Division Multiplexing (OFDM) is considered a key technology in modern wireless-access communication systems. The IEEE 802.16e standard, also denoted as mobile WiMAX, utilizes the MIMO-OFDM technology and it was one of the first initiatives towards the roadmap of fourth generation systems. This paper presents the PHY-layer design, implementation and validation of a high-performance real-time 2x2 MIMO mobile WiMAX transmitter that accounts for low-level deployment issues and signal impairments. The focus is mainly laid on the impact of the selected high bandwidth, which scales the implementation complexity of the baseband signal processing algorithms. The latter also requires an advanced pipelined memory architecture to timely address the datapath operations that involve high memory utilization. We present in this paper a first evaluation of the extracted results that demonstrate the performance of the system using a 2x2 MIMO channel emulation.Postprint (published version

Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis

Field-Programmable Gate Array (FPGA)-based Software-Defined Radio (SDR) is well-suited for experimenting with advanced wireless communication systems, as it allows to alter the architecture promptly while obtaining high performance. However, programming the FPGA using a Hardware Description Language (HDL) is a time-consuming task for FPGA developers and difficult for software developers, which limits the potential of SDR. High-Level Synthesis (HLS) tools aid the designers by allowing them to program on a higher layer of abstraction. However, if not carefully designed, it may lead to a degradation in computing performance or significant increase in resource utilization. This work shows that it is feasible to design modern Orthogonal Frequency Division Multiplex (OFDM) baseband processing modules like channel estimation and equalization using HLS without sacrificing performance and to integrate them in an HDL design to form a fully-operational FPGA-based Wi-Fi (IEEE 802.11a/g/n) transceiver. Starting from no HLS experience, a design with minor overhead in terms of latency and resource utilization as compared to the HDL approach was created in less than one month. We show the readability of the sequential logic as coded in HLS, and discuss the lessons learned from the approach taken and the benefits it brings for further design and experimentation. The FPGA design generated by HLS was verified to be bit-true with its MATLAB implementation in simulation. Furthermore, we show its practical performance when deployed on a System-on-Chip (SoC)-based SDR using a professional wireless connectivity tester.Comment: 7 pages, extended version of poster accepted at FCCM 202