An FPGA implementation of pattern-Selective pyramidal image fusion

The aim of image fusion is to combine multiple images (from one or more sensors) into a single composite image that retains all useful data without introducing artefacts. Pattern-selective techniques attempt to identify and extract whole features in the source images to use in the composite. These techniques usually rely on multiresolution image representations such as Gaussian pyramids, which are localised in both the spatial and spatial-frequency domains, since they enable identification of features at many scales simultaneously. This paper presents an FPGA implementation of pyramidal decomposition and subsequent fusion of dual video streams. This is the first reported instance of a hardware implementation of pattern-selective pyramidal image fusion. Use of FPGA technology has enabled a design that can fuse dual video streams (greyscale VGA, 30fps) in real-time, and provides approximately 100 times speedup over a 2.8GHz Pentium-

FPGA based real-time implementation of Bivariate Empirical Mode Decomposition

A field programmable gate array (FPGA)-based parallel architecture for the real-time and online implementation of the bivariate extension of the empirical mode decomposition (EMD) algorithm is presented. Multivariate extensions of EMD have attracted significant attention in recent years owing to their scope in applications involving multichannel and multidimensional data processing, e.g. biomedical engineering, condition monitoring, image fusion. However, these algorithms are computationally expensive due to the empirical and data-driven nature of these methods. That has hindered the utilisation of EMD, and particularly its bivariate and multivariate extensions, in real-time applications. The proposed parallel architecture is aimed at bridging this gap through real-time computation of the bivariate EMD algorithm. The crux of the architecture is the simultaneous computation of multiple signal projections, locating their local extrema and finally the calculation of their associated complex-valued envelopes for the estimation of local mean. The architecture is implemented on a Xilinx Kintex 7 FPGA and offers significant computational improvements over the existing software-based sequential implementations of bivariate EMD

Design and implementation a prototype system for fusion image by using SWT-PCA algorithm with FPGA technique

The technology of fusion image is dominance strongly over domain research for recent years, the techniques of fusion have various applications in real time used and proposed such as purpose of military and remote sensing etc.,the fusion image is very efficient in processing of digital image. Single image produced from two images or more information of relevant combining process results from multi sensor fusion image. FPGA is the best implementation types of most technology enabling wide spread.This device works with modern versions for different critical characteristics same huge number of elements logic in order to permit complex algorithm implemented. In this paper,filters are designed and implemented in FPGA utilized for disease specified detection from images CT/MRI scanned where the samples are taken for human's brain with various medical images and the processing of fusion employed by using technique Stationary Wavelet Transform and Principal Component Analysis (SWT-PCA). Accuracy image output increases when implemented this technique and that was done by sampling down eliminating where effects blurring and artifacts doesn't influenced. The algorithm of SWT-PCA parameters quality measurements like NCC,MSE ,PSNR, coefficients and Eigen values.The advantages significant of this system that provide real time, time rapid to market and portability beside the change parametric continuing in the DWT transform. The designed and simulation of module proposed system has been done by using MATLAB simulink and blocks generator system, Xilinx synthesized with synthesis tool (XST) and implemented in XilinxSpartan 6-SP605 device

VLSI Implementation of Medical Image Fusion Using DWT-PCA Algorithms

Nowadays, the usage of DIP is more important in the medical field to identify the activities of the patients related to various diseases. Magnetic Resonance Imaging (MRI) and Computer Tomography (CT) scan images are used to perform the fusion process. In brain medical image, MRI scan is used to show the brain structural information without functional data. But, CT scan image is included the functional data with brain activity. To improve the low dose CT scan, hybrid algorithm is introduced in this paper which is implemented in FPGA. The main objective of this work is to optimize performances of the hardware. This work is implemented in FPGA. The combination of Discrete Wavelet Transform (DWT) and Principle Component Analysis (PCA) is known as hybrid algorithm. The Maximum Selection Rule (MSR) is used to select the high frequency component from DWT. These three algorithms have RTL architecture which is implemented by Verilog code. Application Specified Integrated Chips (ASIC) and Field Programmable Gate Array (FPGA) performances analyzed for the different methods. In 180 nm technology, DWT-PCA-IF architecture achieved 5.145 mm2 area, 298.25 mW power, and 124 ms delay. From the fused medical image, mean, Standard Deviation (SD), entropy, and Mutual Information (MI) performances are evaluated for DWT-PCA method

An Efficient Reconfigurable Architecture for Fingerprint Recognition

The fingerprint identification is an efficient biometric technique to authenticate human beings in real-time Big Data Analytics. In this paper, we propose an efficient Finite State Machine (FSM) based reconfigurable architecture for fingerprint recognition. The fingerprint image is resized, and Compound Linear Binary Pattern (CLBP) is applied on fingerprint, followed by histogram to obtain histogram CLBP features. Discrete Wavelet Transform (DWT) Level 2 features are obtained by the same methodology. The novel matching score of CLBP is computed using histogram CLBP features of test image and fingerprint images in the database. Similarly, the DWT matching score is computed using DWT features of test image and fingerprint images in the database. Further, the matching scores of CLBP and DWT are fused with arithmetic equation using improvement factor. The performance parameters such as TSR (Total Success Rate), FAR (False Acceptance Rate), and FRR (False Rejection Rate) are computed using fusion scores with correlation matching technique for FVC2004 DB3 Database. The proposed fusion based VLSI architecture is synthesized on Virtex xc5vlx30T-3 FPGA board using Finite State Machine resulting in optimized parameters