Compiler Implementation for a New Embedded Processor

The department of computer systems in Tampere University of Technology has created an embedded RISC processor, COFFEE, to be used as part of System-on-Chips (SoC). These SoCs include all the hardware a device needs in a single solicon chip. Typically a SoC is constructed from readymade Intellectual Property-blocks (IP-blocks), which are designed to be reusable. A processor is on such block. A processor itself is of very little use. To fully exlploit the potentials of processors, they need a set of software development tools: compiler, assembler, linker, simulator etc. The purpose of this thesis was to develop a high level language compiler for the developed COFFEE RISC core. At first, different ways of reaching this goal was briefly analyzed, and based on that, the retargetable open source Gnu Compiler Compiler Collection (GCC) was chosen to be retargeted to the COFFEE RISC core. The process of retargeting GCC required the generation of a new back-end for it. The back-end consists of a special machine description describing the basic instructions of the processor and C code. A new back-end for GCC was created, and the correctness and performance of the created assembly code was analyzed with basic signal processing algorithms created in C. After initial testing phase, we created some larger applications such as 3D graphich algoriths and a H.264 decoder, which were tested on COFFEE RISC core running in an Altera FPGA prototyping board. /Kir1

Hardware/Software Co-design for Multicore Architectures

Siirretty Doriast