FPGA implementations for parallel multidimensional filtering algorithms

PhD ThesisOne and multi dimensional raw data collections introduce noise and artifacts, which need to be recovered from degradations by an automated filtering system before, further machine analysis. The need for automating wide-ranged filtering applications necessitates the design of generic filtering architectures, together with the development of multidimensional and extensive convolution operators. Consequently, the aim of this thesis is to investigate the problem of automated construction of a generic parallel filtering system. Serving this goal, performance-efficient FPGA implementation architectures are developed to realize parallel one/multi-dimensional filtering algorithms. The proposed generic architectures provide a mechanism for fast FPGA prototyping of high performance computations to obtain efficiently implemented performance indices of area, speed, dynamic power, throughput and computation rates, as a complete package. These parallel filtering algorithms and their automated generic architectures tackle the major bottlenecks and limitations of existing multiprocessor systems in wordlength, input data segmentation, boundary conditions as well as inter-processor communications, in order to support high data throughput real-time applications of low-power architectures using a Xilinx Virtex-6 FPGA board. For one-dimensional raw signal filtering case, mathematical model and architectural development of the generalized parallel 1-D filtering algorithms are presented using the 1-D block filtering method. Five generic architectures are implemented on a Virtex-6 ML605 board, evaluated and compared. A complete set of results on area, speed, power, throughput and computation rates are obtained and discussed as performance indices for the 1-D convolution architectures. A successful application of parallel 1-D cross-correlation is demonstrated. For two dimensional greyscale/colour image processing cases, new parallel 2-D/3-D filtering algorithms are presented and mathematically modelled using input decimation and output image reconstruction by interpolation. Ten generic architectures are implemented on the Virtex-6 ML605 board, evaluated and compared. Key results on area, speed, power, throughput and computation rate are obtained and discussed as performance indices for the 2-D convolution architectures. 2-D image reconfigurable processors are developed and implemented using single, dual and quad MAC FIR units. 3-D Colour image processors are devised to act as 3-D colour filtering engines. A 2-D cross-correlator parallel engine is successfully developed as a parallel 2-D matched filtering algorithm for locating any MRI slice within a MRI data stack library. Twelve 3-D MRI filtering operators are plugged in and adapted to be suitable for biomedical imaging, including 3-D edge operators and 3-D noise smoothing operators. Since three dimensional greyscale/colour volumetric image applications are computationally intensive, a new parallel 3-D/4-D filtering algorithm is presented and mathematically modelled using volumetric data image segmentation by decimation and output reconstruction by interpolation, after simultaneously and independently performing 3-D filtering. Eight generic architectures are developed and implemented on the Virtex-6 board, including 3-D spatial and FFT convolution architectures. Fourteen 3-D MRI filtering operators are plugged and adapted for this particular biomedical imaging application, including 3-D edge operators and 3-D noise smoothing operators. Three successful applications are presented in 4-D colour MRI (fMRI) filtering processors, k-space MRI volume data filter and 3-D cross-correlator.IRAQI Government

Proposta de um Sistema de Tomada de Decisão para Detecção de Veículos em Movimento para FPGA

Os métodos pesquisados para detecção de objetos em movimento através do processamento de imagens em processadores de uso geral (General Purpose Processors - GPPs) apresentam, em sua maioria, uma abordagem que não permite uma implementação com bons resultados em matriz de portas programável em campo (Field Programmable Gate Array-FPGA). Isso ocorre devido à classificação correta dos pixels estar diretamente relacionada à implementação de técnicas mais complexas para modelar a imagem de referência e que requerem muitos recursos em termos de memória. Além disso, quase todos os métodos analisados realizam apenas o processamento da tomada de decisão clássica, sendo poucas as propostas que baseiam sua tomada de decisão na integral fuzzy. Assim, visando melhorar a classificação dos pixels durante o processo de detecção de veículos em movimento é proposta uma abordagem que realiza a fusão das tomadas de decisão fuzzy e clássica combinando técnicas convencionais de processamento digital de imagens. Dessa forma, o sistema de tomada de decisão proposto para detectar os veículos em movimento busca não comprometer os resultados em termos de classificação dos pixels mesmo utilizando um a técnica de modelagem simples para obter a imagem de referência. Essa imagem é obtida através da estimativa do valor mediano e possibilita que o sistema de detecção de veículos em movimento proposto não precise do armazenamento de várias imagens para obter a imagem de referência. Os resultados são verificados em termos de recursos ocupados, frequência máxima de operação e classificação dos pixels em FPGAs de baixo custo. Além disso, os resultados em termos de classificação dos pixels são comparados através de várias medidas com outros métodos, apresentando resultados promissores no processamento de imagens em tempo real em FPGAs de baixo custo