Acceleration of Spiking Neural Networks on Multicore Architectures

The human cortex is the seat of learning and cognition. Biological scale implementations of cortical models have the potential to provide significantly more power problem solving capabilities than traditional computing algorithms. The large scale implementation and design of these models has attracted significant attention recently. High performance implementations of the models are needed to enable such large scale designs. This thesis examines the acceleration of the spiking neural network class of cortical models on several modern multicore processors. These include the Izhikevich, Wilson, Morris-Lecar, and Hodgkin-Huxley models. The architectures examined are the STI Cell, Sun UltraSPARC T2+, and Intel Xeon E5345. Results indicate that these modern multicore processors can provide significant speed-ups and thus are useful in developing large scale cortical models. The models are then implemented on a 50 TeraFLOPS 336 node PlayStation 3 cluster. Results indicate that the models scale well on this cluster and can emulate 108 neurons and 1010 synapses. These numbers are comparable to the large scale cortical model implementation studies performed by IBM using the Blue Gene/L supercomputer. This study indicates that a cluster of PlayStation 3s can provide an economical, yet powerful, platform for simulating large scale biological models

Principles of Neuromorphic Photonics

In an age overrun with information, the ability to process reams of data has become crucial. The demand for data will continue to grow as smart gadgets multiply and become increasingly integrated into our daily lives. Next-generation industries in artificial intelligence services and high-performance computing are so far supported by microelectronic platforms. These data-intensive enterprises rely on continual improvements in hardware. Their prospects are running up against a stark reality: conventional one-size-fits-all solutions offered by digital electronics can no longer satisfy this need, as Moore's law (exponential hardware scaling), interconnection density, and the von Neumann architecture reach their limits. With its superior speed and reconfigurability, analog photonics can provide some relief to these problems; however, complex applications of analog photonics have remained largely unexplored due to the absence of a robust photonic integration industry. Recently, the landscape for commercially-manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. The scientific community has set out to build bridges between the domains of photonic device physics and neural networks, giving rise to the field of \emph{neuromorphic photonics}. This article reviews the recent progress in integrated neuromorphic photonics. We provide an overview of neuromorphic computing, discuss the associated technology (microelectronic and photonic) platforms and compare their metric performance. We discuss photonic neural network approaches and challenges for integrated neuromorphic photonic processors while providing an in-depth description of photonic neurons and a candidate interconnection architecture. We conclude with a future outlook of neuro-inspired photonic processing.Comment: 28 pages, 19 figure

Gyrification, cortical and subcortical morphometry in neurofibromatosis type 1: an uneven profile of developmental abnormalities.

Background: Neurofibromatosis type 1 (NF1) is a monogenic disorder associated with cognitive impairments. In order to understand how mutations in the NF1 gene impact brain structure it is essential to characterize in detail the brain structural abnormalities in patients with NF1. Previous studies have reported contradictory findings and have focused only on volumetric measurements. Here, we investigated the volumes of subcortical structures and the composite dimensions of the cortex through analysis of cortical volume, cortical thickness, cortical surface area and gyrification. Methods: We studied 14 children with NF1 and 14 typically developing children matched for age, gender, IQ and right/left-handedness. Regional subcortical volumes and cortical gyral measurements were obtained using the FreeSurfer software. Between-group differences were evaluated while controlling for the increase in total intracranial volume observed in NF1. Results: Subcortical analysis revealed disproportionately larger thalami, right caudate and middle corpus callosum in patients with NF1. Cortical analyses on volume, thickness and surface area were however not indicative of significant alterations in patients. Interestingly, patients with NF1 had significantly lower gyrification indices than typically developing children primarily in the frontal and temporal lobes, but also affecting the insula, cingulate cortex, parietal and occipital regions. Conclusions: The neuroanatomic abnormalities observed were localized to specific brain regions, indicating that particular areas might constitute selective targets for NF1 gene mutations. Furthermore, the lower gyrification indices were accompanied by a disproportionate increase in brain size without the corresponding increase in folding in patients with NF1. Taken together these findings suggest that specific neurodevelopmental processes, such as gyrification, are more vulnerable to NF1 dysfunction than others. The identified changes in brain organization are consistent with the patterns of cognitive dysfunction in the NF1 phenotype. © 2013 Violante et al

Accelerating Pattern Recognition Algorithms On Parallel Computing Architectures

The move to more parallel computing architectures places more responsibility on the programmer to achieve greater performance. The programmer must now have a greater understanding of the underlying architecture and the inherent algorithmic parallelism. Using parallel computing architectures for exploiting algorithmic parallelism can be a complex task. This dissertation demonstrates various techniques for using parallel computing architectures to exploit algorithmic parallelism. Specifically, three pattern recognition (PR) approaches are examined for acceleration across multiple parallel computing architectures, namely field programmable gate arrays (FPGAs) and general purpose graphical processing units (GPGPUs). Phase-only filter correlation for fingerprint identification was studied as the first PR approach. This approach\u27s sensitivity to angular rotations, scaling, and missing data was surveyed. Additionally, a novel FPGA implementation of this algorithm was created using fixed point computations, deep pipelining, and four computation phases. Communication and computation were overlapped to efficiently process large fingerprint galleries. The FPGA implementation showed approximately a 47 times speedup over a central processing unit (CPU) implementation with negligible impact on precision. For the second PR approach, a spiking neural network (SNN) algorithm for a character recognition application was examined. A novel FPGA implementation of the approach was developed incorporating a scalable modular SNN processing element (PE) to efficiently perform neural computations. The modular SNN PE incorporated streaming memory, fixed point computation, and deep pipelining. This design showed speedups of approximately 3.3 and 8.5 times over CPU implementations for 624 and 9,264 sized neural networks, respectively. Results indicate that the PE design could scale to process larger sized networks easily. Finally for the third PR approach, cellular simultaneous recurrent networks (CSRNs) were investigated for GPGPU acceleration. Particularly, the applications of maze traversal and face recognition were studied. Novel GPGPU implementations were developed employing varying quantities of task-level, data-level, and instruction-level parallelism to achieve efficient runtime performance. Furthermore, the performance of the face recognition application was examined across a heterogeneous cluster of multi-core and GPGPU architectures. A combination of multi-core processors and GPGPUs achieved roughly a 996 times speedup over a single-core CPU implementation. From examining these PR approaches for acceleration, this dissertation presents useful techniques and insight applicable to other algorithms to improve performance when designing a parallel implementation

Advanced spike sorting approaches in implantable VLSI wireless brain computer interfaces: a survey

Brain Computer/Machine Interfaces (BCI/BMIs) have substantial potential for enhancing the lives of disabled individuals by restoring functionalities of missing body parts or allowing paralyzed individuals to regain speech and other motor capabilities. Due to severe health hazards arising from skull incisions required for wired BCI/BMIs, scientists are focusing on developing VLSI wireless BCI implants using biomaterials. However, significant challenges, like power efficiency and implant size, persist in creating reliable and efficient wireless BCI implants. With advanced spike sorting techniques, VLSI wireless BCI implants can function within the power and size constraints while maintaining neural spike classification accuracy. This study explores advanced spike sorting techniques to overcome these hurdles and enable VLSI wireless BCI/BMI implants to transmit data efficiently and achieve high accuracy.Comment: Submitted to 37th International Conference on VLSI Design 202