Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications

Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitations come from two directions: commercial Field Programmable Analog Arrays (FPAA) have limited variability in the components offered on-chip; and they are only qualified for best case scenarios for military grade (-55C to +125C). In order to avoid huge overheads, there is a growing trend towards avoiding thermal and radiation protection by developing extreme environment electronics, which maintain correct operation while exposed to temperature extremes (-180degC to +125degC). This paper describes a recent FPAA design, the Self-Reconfigurable Analog Array (SRAA) developed at JPL. It overcomes both limitations, offering a variety of analog cells inside the array together with the possibility of self-correction at extreme temperatures

Challenging the evolutionary strategy for synthesis of analogue computational circuits

There are very few reports in the past on applications of Evolutionary Strategy (ES) towards the synthesis of analogue circuits. Moreover, even fewer reports are on the synthesis of computational circuits. Last fact is mainly due to the dif-ficulty in designing of the complex nonlinear functions that these circuits perform. In this paper, the evolving power of the ES is challenged to design four computational circuits: cube root, cubing, square root and squaring functions. The synthesis succeeded due to the usage of oscillating length genotype strategy and the substructure reuse. The approach is characterized by its simplicity and represents one of the first attempts of application of ES towards the synthesis of “QR” circuits. The obtained experimental results significantly exceed the results published before in terms of the circuit quality, economy in components and computing resources utilized, revealing the great potential of the technique pro-posed to design large scale analog circuits

Funding and Strategic Alignment Guidance for Infusing Small Business Innovation Research Technology Into Human Exploration and Operations Mission Directorate Projects for 2016

This report is intended to help NASA program and project managers incorporate Small Business Innovation Research Small Business Technology Transfer (SBIR/STTR) technologies into NASA Human Exploration and Operations Mission Directorate (HEOMD) projects. Other Government and commercial projects managers can also find this useful. Space Transportation; Life Support and Habitation Systems; Extra-Vehicular Activity; High EfficiencySpace Power; Human Exploration and Operations Mission

Building an Economical and Sustainable Lunar Infrastructure to Enable Lunar Industrialization

A new concept study was initiated to examine the architecture needed to gradually develop an economical, evolvable and sustainable lunar infrastructure using a public/private partnerships approach. This approach would establish partnership agreements between NASA and industry teams to develop a lunar infrastructure system that would be mutually beneficial. This approach would also require NASA and its industry partners to share costs in the development phase and then transfer operation of these infrastructure services back to its industry owners in the execution phase. These infrastructure services may include but are not limited to the following: lunar cargo transportation, power stations, communication towers and satellites, autonomous rover operations, landing pads and resource extraction operations. The public/private partnerships approach used in this study leveraged best practices from NASA's Commercial Orbital Transportation Services (COTS) program which introduced an innovative and economical approach for partnering with industry to develop commercial cargo services to the International Space Station. This program was planned together with the ISS Commercial Resupply Services (CRS) contracts which was responsible for initiating commercial cargo delivery services to the ISS for the first time. The public/private partnerships approach undertaken in the COTS program proved to be very successful in dramatically reducing development costs for these ISS cargo delivery services as well as substantially reducing operational costs. To continue on this successful path towards installing economical infrastructure services for LEO and beyond, this new study, named Lunar COTS (Commercial Operations and Transport Services), was conducted to examine extending the NASA COTS model to cis-lunar space and the lunar surface. The goals of the Lunar COTS concept are to: 1) develop and demonstrate affordable and commercial cis-lunar and surface capabilities, such as lunar cargo delivery and surface power generation, in partnership with industry; 2) incentivize industry to establish economical and sustainable lunar infrastructure services to support NASA missions and initiate lunar commerce; and 3) encourage creation of new space markets for economic growth and benefit. A phased-development approach was also studied to allow for incremental development and demonstration of capabilities needed to build a lunar infrastructure. This paper will describe the Lunar COTS concept goals, objectives and approach for building an economical and sustainable lunar infrastructure. It will also describe the technical challenges and advantages of developing and operating each infrastructure element. It will also describe the potential benefits and progress that can be accomplished in the initial phase of this Lunar COTS approach. Finally, the paper will also look forward to the potential of a robust lunar industrialization environment and its potential effect on the next 50 years of space exploration

Automatic design of analogue circuits

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Evolvable Hardware (EHW) is a promising area in electronics today. Evolutionary Algorithms (EA), together with a circuit simulation tool or real hardware, automatically designs a circuit for a given problem. The circuits evolved may have unconventional designs and be less dependent on the personal knowledge of a designer. Nowadays, EA are represented by Genetic Algorithms (GA), Genetic Programming (GP) and Evolutionary Strategy (ES). While GA is definitely the most popular tool, GP has rapidly developed in recent years and is notable by its outstanding results. However, to date the use of ES for analogue circuit synthesis has been limited to a few applications. This work is devoted to exploring the potential of ES to create novel analogue designs. The narrative of the thesis starts with a framework of an ES-based system generating simple circuits, such as low pass filters. Then it continues with a step-by-step progression to increasingly sophisticated designs that require additional strength from the system. Finally, it describes the modernization of the system using novel techniques that enable the synthesis of complex multi-pin circuits that are newly evolved. It has been discovered that ES has strong power to synthesize analogue circuits. The circuits evolved in the first part of the thesis exceed similar results made previously using other techniques in a component economy, in the better functioning of the evolved circuits and in the computing power spent to reach the results. The target circuits for evolution in the second half are chosen by the author to challenge the capability of the developed system. By functioning, they do not belong to the conventional analogue domain but to applications that are usually adopted by digital circuits. To solve the design tasks, the system has been gradually developed to support the ability of evolving increasingly complex circuits. As a final result, a state-of-the-art ES-based system has been developed that possesses a novel mutation paradigm, with an ability to create, store and reuse substructures, to adapt the mutation, selection parameters and population size, utilize automatic incremental evolution and use the power of parallel computing. It has been discovered that with the ability to synthesis the most up-to-date multi-pin complex analogue circuits that have ever been automatically synthesized before, the system is capable of synthesizing circuits that are problematic for conventional design with application domains that lay beyond the conventional application domain for analogue circuits

Design and Implementation of a High Temperature Fully-Integrated BCD-on-SOI Under Voltage Lock Out Circuit

As concern about the environment has grown in recent years, alternatives in the automotive industry have become an important topic for researchers. One alternative being considered is electric vehicles, which utilize electric motors. DC/AC inverters and DC/DC power converters control these electric motors. A logic circuit is needed to power these converters; however, the logic generators inherently operate at a voltage too low to power the motors. A device known as the gate driver is the interface between the logic generators (or microcontroller) and the power devices (power converter). The gate driver provides the power needed to drive the power devices. Circuits are susceptible to voltage and temperature changes though. For this reason, protection circuits must be implemented as an integral part of the gate driver circuits. The Under Voltage Lock Out (UVLO) circuit provides important detection of under voltage conditions in the power supply thus preventing malfunctions. There are multiple power supplies in the gate driver circuit, and it is important to monitor all of these supplies for both surges and reductions in power. If the power supply should drop below the threshold (nominally 80%) there could be issues in the gate driver’s functionality. Since the gate driver will be located under the hood of a hybrid electric vehicles, operating temperatures can reach extremely high values. For this reason, circuit designs must provide reliable operation of the circuits in an extreme environment

Fault-tolerant evolvable hardware using field-programmable transistor arrays

The paper presents an evolutionary approach to the design of fault-tolerant VLSI (very large scale integrated) circuits using EHW (evolvable hardware). The EHW research area comprises a set of applications where GA (genetic algorithms) are used for the automatic synthesis and adaptation of electronic circuits. EHW is particularly suitable for applications requiring changes in task requirements and in the environment or faults, through its ability to reconfigure the hardware structure dynamically and autonomously. This capacity for adaptation is achieved via the use of GA search techniques, in our experiments, a fine-grained CMOS (complementary metal-oxide silicon) FPTA (field-programmable FPGA transistor array) architecture is used to synthesize electronic circuits. The FPTA is a reconfigurable architecture, programmable at the transistor level and specifically designed for EHW applications. The paper demonstrates the power of EA to design analog and digital fault-tolerant circuits. It compares two methods to achieve fault-tolerant design, one based on fitness definition and the other based on population. The fitness approach defines, explicitly, the faults that the component can encounter during its life, and evaluates the average behavior of the individuals. The population approach, on the other hand, uses the implicit information of the population statistics accumulated by the GA over many generations. The paper presents experiment results obtained using both approaches for the synthesis of a fault-tolerant digital circuit (XNOR) and a fault-tolerant analog circuit (multiplier)

Viability of a Reusable In-Space Transportation System

The National Aeronautics and Space Administration (NASA) is currently developing options for an Evolvable Mars Campaign (EMC) that expands human presence from Low Earth Orbit (LEO) into the solar system and to the surface of Mars. The Hybrid in-space transportation architecture is one option being investigated within the EMC. The architecture enables return of the entire in-space propulsion stage and habitat to cis-lunar space after a round trip to Mars. This concept of operations opens the door for a fully reusable Mars transportation system from cis-lunar space to a Mars parking orbit and back. This paper explores the reuse of in-space transportation systems, with a focus on the propulsion systems. It begins by examining why reusability should be pursued and defines reusability in space-flight context. A range of functions and enablers associated with preparing a system for reuse are identified and a vision for reusability is proposed that can be advanced and implemented as new capabilities are developed. Following this, past reusable spacecraft and servicing capabilities, as well as those currently in development are discussed. Using the Hybrid transportation architecture as an example, an assessment of the degree of reusability that can be incorporated into the architecture with current capabilities is provided and areas for development are identified that will enable greater levels of reuse in the future. Implications and implementation challenges specific to the architecture are also presented