Evolving Combinational Logic Circuits Using a Hybrid Quantum Evolution and Particle Swarm Inspired Algorithm

In this paper, an algorithm inspired from quantum evolution and particle swarm to evolve combinational logic circuits is presented. This algorithm uses the framework of the local version of particle swarm optimization with quantum evolutionary algorithms, and integer encoding. A multi-objective fitness function is used to evolve the combinational logic circuits in order obtain feasible circuits with minimal number of gates in the design. A comparative study indicates the superior performance of the hybrid quantum evolution-particle swarm inspired algorithm over the particle swarm and other evolutionary algorithms (such as genetic algorithms) independently

Evolving Combinational Logic Circuits Using a Hybrid Quantum Evolution and Particle Swarm Inspired Algorithm

An algorithm inspired from quantum evolution and particle swarm optimization is used to evolve combinational logic circuits. This algorithm uses the framework of the local version of particle swarm optimizations with quantum evolutionary algorithms, and integer encoding. A multi-objective fitness function is used to evolve the digital circuits in order to obtain a variety of feasible circuits with minimal number of gates in the design. A comparative study indicates the superior performance of the hybrid quantum evolution-particle swarm inspired algorithm over the particle swarm and other evolutionary algorithms (such as genetic algorithms) independently

Generalized disjunction decomposition for the evolution of programmable logic array structures

Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has shown one of its main deficiencies, when applied to solving real world applications, to be scalability. In the past few years several techniques have been proposed to avoid and/or solve this problem. Generalized disjunction decomposition (GDD) is one of these proposed methods. GDD was successful for the evolution of large combinational logic circuits based on a FPGA structure when used together with bi-directional incremental evolution and with (1+ë) evolution strategy. In this paper a modified generalized disjunction decomposition, together with a recently introduced multi-population genetic algorithm, are implemented and tested for its scalability for solving large combinational logic circuits based on Programmable Logic Array (PLA) structures

Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness

We use evolutionary search to design combinational logic circuits. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells whose dimension is defined by the circuit layout. The main idea of this approach is to improve quality of the circuits evolved by the GA by reducing the number of active gates used. We accomplish this by combining two ideas: 1) using multi-objective fitness function; 2) evolving circuit layout. It will be shown that using these two approaches allows us to increase the quality of evolved circuits. The circuits are evolved in two phases. Initially the genome fitness in given by the percentage of output bits that are correct. Once 100% functional circuits have been evolved, the number of gates actually used in the circuit is taken into account in the fitness function. This allows us to evolve circuits with 100% functionality and minimise the number of active gates in circuit structure. The population is initialised with heterogeneous circuit layouts and the circuit layout is allowed to vary during the evolutionary process. Evolving the circuit layout together with the function is one of the distinctive features of proposed approach. The experimental results show that allowing the circuit layout to be flexible is useful when we want to evolve circuits with the smallest number of gates used. We find that it is better to use a fixed circuit layout when the objective is to achieve the highest number of 100% functional circuits. The two-fitness strategy is most effective when we allow a large number of generations

A New Evolutionary Hardware Approach for Logic Design.

This poster paper summarizes ongoing dissertation research defining an evolvable hardware methodology for evolving combinational binary and multiple-valued logic circuits. This dissertation provides an overview of current evolvable hardware approaches; defines the combinational logic design problem; describes the gate and function level evolvable hardware technique; and develops a new methodology for evolving binary and multiple-valued combinational logic circuits with and without automatically defined functions. The new methodology promises significant improvements over current conventional algebraic techniques

Generalized disjunction decomposition for evolvable hardware

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the “generalized disjunction decomposition” (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the$(1 + lambda)$evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided

An extrinsic function-level evolvable hardware approach

The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in first time. The new representation of logic gate in extrinsic EHW allows us to describe behaviour of any multi-input multi-output logic function. The circuit is represented in the form of connections and functionalities of a rectangular array of building blocks. Each building block can implement primitive logic function or any multi-input multi-output logic function defined in advance. The method has been tested on evolving logic circuits using half adder, full adder and multiplier. The effectiveness of this approach is investigated for multiple-valued and binary arithmetical functions. For these functions either method appears to be much more efficient than similar approach with two-input one-output cell representation

On evolution of relatively large combinational logic circuits

Evolvable hardware (EHW) (Yao and Higuchi, 1999) is a technique introduced to automatically design circuits where the circuit configuration is carried out by evolutionary algorithms. One of the main difficulties in using EHW to solve real-world problems is the scalability. Until now, several strategies have been proposed to avoid this problem, but none of them completely tackle the issue. In this paper three different methods for evolving the most complex circuits have been tested for their scalability. These methods are bi-directional incremental evolution (SO-BIE); generalised disjunction decomposition (GD-BIE) and evolutionary strategies (ES) with dynamic mutation rate. In order to achieve the generalised conclusions the chosen approaches were tested using multipliers, traditionally used in EHW, but also logic circuits taken from MCNC (Yang, 1991) benchmark library and randomly generated circuits. The analysis of the approaches demonstrated that PLA-based ES is capable of evolving logic circuits of up to 12 inputs. The use of SO-BIE allows the generation of fully functional circuits of 14 inputs and GD-BIE is estimated to be able to evolve circuits of 21 inputs

Assembling strategies in extrinsic evolvable hardware with bi-directional incremental evolution

Bidirectional incremental evolution (BIE) has been proposed as a technique to overcome the ”stalling” effect in evolvable hardware applications. However preliminary results show perceptible dependence of performance of BIE and quality of evaluated circuit on assembling strategy applied during reverse stage of incremental evolution. The purpose of this paper is to develop assembling strategy that will assist BIE to produce relatively optimal solution with minimal computational effort (e.g. the minimal number of generations)