Embedded CMOS Basecalling for Nanopore DNA Sequencing

DNA sequencing is undergoing a profound evolution into a mobile technology. Unfortunately the effort needed to process the data emerging from this new sequencing technology requires a compute power only available to traditional desktop or cloud-based machines. To empower the full potential of portable DNA solutions a means of efficiently carrying out their computing needs in an embedded format will certainly be required. This thesis presents the design of a custom fixed-point VLSI hardware implementation of an HMM-based multi-channel DNA sequence processor. A 4096 state (6-mer nanopore sensor) basecalling architecture is designed in a 32-nm CMOS technology with the ability to process 1 million DNA base pairs per second per channel. Over a 100 mm^2 silicon footprint the design could process the equivalent of one human genome every 30 seconds at a power consumption of around 5 W

High frequency AC power converter for low voltage circuits

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 74-76).This thesis presents a novel AC power delivery architecture that is suitable for VHF frequency (50-100MHz) polyphase AC/DC power conversion in low voltage integrated circuits. A complete AC power delivery architecture was evaluated demonstrating the benefits of delivering power across the interconnect at high voltage and lower current with on- or over-die transformation to low voltage and high current. Two approaches to polyphase matching networks in the transformation stage are compared: a 3-phase system with separate single-phase matching networks and individual full bridge rectifiers, and a 3-phase delta-to-wye matching network and a 3-phase rectifier bridge. In addition, a novel switch-capacitor rectifier capable of 3V, 1W output, was evaluated as an alternative circuit to the diode rectifiers. A 50MHz prototype of each version of the system was designed and built for a 12:1 conversion ratio with 24Vpp line-to-line AC input, 2V DC output and 0.7W output power. The measured overall system efficiency is about 63 % for the 3-phase delta system. Although the application is intended for an integrated CMOS implementation, this thesis primarily focuses on discrete PCB level realizations of the proposed architectures to validate the concept and provide insights for future designs.by Nathaniel Jay Tobias Salazar.M.Eng

Very-high-frequency low-voltage power delivery

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 217-223).Power conversion for the myriad low-voltage electronic circuits in use today, including portable electronic devices, digital electronics, sensors and communication circuits, is becoming increasingly challenging due to the desire for lower voltages, higher conversion ratios and higher bandwidth. Future computation systems also pose a major challenge in energy delivery that is difficult to meet with existing devices and design strategies. To reduce interconnect bottlenecks and enable more flexible energy utilization, it is desired to deliver power across interconnects at high voltage and low current with on- or over-die transformation to low voltage and high current, while providing localized voltage regulation in numerous zones. This thesis introduces elements for hybrid GaN-Si dc-de power converters operating at very high frequencies (VHF, 30-300 MHz) for low-voltage applications. Contributions include development of a new VHF frequency multiplier inverter suitable for step-down power conversion, and a Si CMOS switched-capacitor step-down rectifier. These are applied to develop a prototype GaN-Si hybrid dc-dc converter operating at 50 MHz. Additionally, this thesis exploits these elements to propose an ac power delivery architecture for low-voltage electronics in which power is delivered across the interconnect to the load at VHF ac, with local on-die transformation and rectification to dc. With the proposed technologies and emerging passives, it is predicted that the ac power delivery system can achieve over 90 % efficiency with greater than 1 W/mm² power density and 5:1 voltage conversion ratio. A prototype system has been designed and fabricated using a TSMC 0.25 [mu]m CMOS process to validate the concept. It operates at 50 MHz with output power of 4 W. The prototype converter has 8:1 voltage conversion ratio with input voltage of 20 V and output voltage of 2.5 V. To the author's best knowledge, this is the first ac power delivery architecture for low-voltage electronics ever built and tested.by Wei Li.Ph.D