Advancing the performance of one-dimensional photonic crystal/photonic wire micro-cavities in silicon-on-insulator

We present new results that demonstrate advances in the performance achievable in photonic crystal/photonic wire micro-cavities. In one example, a quality-factor value as high as 147,000 has been achieved experimentally at a useful transmission level

Step and flash imprint lithography: materials and process development

textStep and flash imprint lithography (SFIL) is a high resolution, low cost patterning technique developed at The University of Texas at Austin. Envisioned as an alternative to conventional photolithographic techniques currently used to pattern semiconductor substrates, SFIL utilizes photocurable monomers in a micromolding process to replicate features etched into a transparent template. The elimination of expensive projection optics and sources required for photolithography offers tremendous potential cost savings. This dissertation presents an overview of the SFIL process and provides a description of each process step. Particular attention is paid to development of SFIL compatible etch processes as well as to the effects of polymerization induced densification on feature profile. Modeling of polymerization induced feature shrinkage and simulation of line profiles during etch processing are also presented.Chemical Engineerin

Materials and processes for advanced lithography applications

textStep and Flash Imprint Lithography (S-FIL) is a high resolution, next-generation lithography technique that uses an ambient temperature and low pressure process to replicate high resolution images in a UV-curable liquid material. Application of the S-FIL process in conjunction with multi-level imprint templates and new imprint materials enables one S-FIL step to reproduce the same structures that require two photolithography steps, thereby greatly reducing the number of patterning steps required for the copper, dual damascene process used to fabricate interconnect wirings in modern integrated circuits. Two approaches were explored for the implementation of S-FIL in the dual damascene process: sacrificial imprint materials and imprintable dielectric materials. Sacrificial imprint materials function as a pattern recording medium during S-FIL and a three-dimensional etch mask during the dielectric substrate etch, enabling the simultaneous patterning of both the via and metal structures in the dielectric substrate. Development of sacrificial imprint materials and the associated imprint and etch processes are described. Application of S-FIL and the sacrificial imprint material in a commercial copper dual damascene process successfully produced functional copper interconnect structures, demonstrating the feasibility of integrating multi-level S-FIL in the copper dual damascene process. Imprintable dielectric materials are designed to combine the multi-level patterning capability of S-FIL with novel dielectric precursor materials, enabling the simultaneous deposition and patterning of the interlayer dielectric material. Several candidate imprintable dielectric materials were evaluated: sol-gel, polyhedral oligomeric silsesquioxane (POSS) epoxide, POSS acrylate, POSS azide, and POSS thiol. POSS thiol shows the most promise as functional imprintable dielectric material, although additional work in the POSS thiol formulation and viscous dispense process are needed to produce functional interconnect structures. Integration of S-FIL with imprintable dielectric materials would enable further streamlining of the dual damascene fabrication process. The fabrication of electronic devices on flexible substrates represents an opportunity for the development of macroelectronics such as flexible displays and large area devices. Traditional optical lithography encounters alignment and overlay limitations when applied on flexible substrates. A thermally activated, dual-tone photoresist system and its associated etch process were developed to enable the simultaneous patterning of two device layers on a flexible substrate.Chemical Engineerin

Post Exposure Silyation of a Positive Photoresist

A silylation process employing hexamethyldisilazane (HMDS\u3e as a silylating agent was examined as a ethod of combining the high resolution capabilities of a multilevel resist and the process simplicity of a single layer resist scheme. Atmospheric pressure vapor phase silylation and liquid phase silylation were performed on Kodak 809 Micropositive resist. The vapor phase silylation did not result in significant alteration of the etch characteristics. The liquid phase silylation was performed for several HMDS concentrations in Freon. Liquid phase silylation was shown to provide significant etch selectivity upon exposure to an oxygen plasma

Low-cost interference lithography

The authors report demonstration of a low-cost ( ∼ 1000 USD) interference lithography system based on a Lloyd’s mirror interferometer that is capable of ∼ 300 nm pitch patterning. The components include only a 405 nm GaN diode-laser module, a machinist’s block, a chrome-coated silicon mirror, substrate, and double-sided carbon scanning electron microscopy (SEM) tape. The laser and the machinist’s block were assembled in a linear configuration, and to complete the system, the mirror and substrate were taped to perpendicular surfaces of the machinist’s block. Approximately 50 silicon substrates were prepared, exposed, and developed, after which some were inspected in a SEM. The associated laser spectrum was also measured, enabling calculation of the laser’s fringe visibility as it varied along the substrate surface. To compare the exposed resist pattern to the fringe visibility, the authors measured the first order diffraction efficiency as a function of position along the grating surface. Their measurements indicated that artifacts seen in both the optical spectrum and resulting grating patterns arose from the laser diode source, thus improving the source characteristics will be the topic of future work.Singapore-MIT Alliance for Research and Technolog

Sub 20 nm Silicon Patterning and Metal Lift-Off Using Thermal Scanning Probe Lithography

The most direct definition of a patterning process' resolution is the smallest half-pitch feature it is capable of transferring onto the substrate. Here we demonstrate that thermal Scanning Probe Lithography (t-SPL) is capable of fabricating dense line patterns in silicon and metal lift-off features at sub 20 nm feature size. The dense silicon lines were written at a half pitch of 18.3 nm to a depth of 5 nm into a 9 nm polyphthalaldehyde thermal imaging layer by t-SPL. For processing we used a three-layer stack comprising an evaporated SiO2 hardmask which is just 2-3 nm thick. The hardmask is used to amplify the pattern into a 50 nm thick polymeric transfer layer. The transfer layer subsequently serves as an etch mask for transfer into silicon to a nominal depth of 60 nm. The line edge roughness (3 sigma) was evaluated to be less than 3 nm both in the transfer layer and in silicon. We also demonstrate that a similar three-layer stack can be used for metal lift-off of high resolution patterns. A device application is demonstrated by fabricating 50 nm half pitch dense nickel contacts to an InAs nanowire.Comment: 7 pages, 5 figures, to be published in JVST

Lithographic performance of ZEP520A and mr-PosEBR resists exposed by electron beam and extreme ultraviolet lithography

Pattern transfer by deep anisotropic etch is a well-established technique for fabrication of nanoscale devices and structures. For this technique to be effective, the resist material plays a key role and must have high resolution, reasonable sensitivity and high etch selectivity against the conventional silicon substrate or underlayer film. In this work, the lithographic performance of two high etch resistance materials was evaluated: ZEP520A (Nippon Zeon Co.) and mr-PosEBR (micro resist technology GmbH). Both materials are positive tone, polymer-based and non-chemically amplified resists. Two exposure techniques were used: electron beam lithography (EBL) and extreme ultraviolet (EUV) lithography. These resists were originally designed for EBL patterning, where high quality patterning at sub-100 nm resolution was previously demonstrated. In the scope of this work, we also aim to validate their extendibility to EUV for high resolution and large area patterning. To this purpose, the same EBL process conditions were employed at EUV. The figures of merit, i.e. dose to clear, dose to size, and resolution, were extracted and these results are discussed systematically. It was found that both materials are very fast at EUV (dose to clear lower than 12 mJ/cm2) and are capable of resolving dense lines/space arrays with a resolution of 25 nm half-pitch. The quality of patterns was also very good and the sidewall roughness was below 6 nm. Interestingly, the general-purpose process used for EBL can be extended straightforwardly to EUV lithography with comparable high quality and yield. Our findings open new possibilities for lithographers who wish to devise novel fabrication schemes exploiting EUV for fabrication of nanostructures by deep etch pattern transfer.Comment: 20 pages, 4 figures, 3 table