Processor Enhancements for Media Streaming Applications

The development of more processing demanding applications on the Internet (video broadcasting) on one hand and the popularity of recent devices at the user level (digital cameras, wireless videophones, ...) on the other hand introduce challenges at several levels. Today, such devices present processing capabilities and bandwidth settings that are inefficient to manage scalable QoS requirements in a typical media delivery framework. In this paper, we present an impact study of such a scalable data representation optimized for QoS (Matching Pursuit 3D algorithms) on processor architectures to achieve the best performance and power efficiency. A review of state of the art techniques for processor architecture enhancement let us expect promising opportunities from the latest developments in the reconfigurable computing research field. We present here the first design steps of an efficient reconfigurable coprocessor especially designed to cope with future video delivery and multimedia processing requirements. Architecture perspectives are proposed with respect to low development cost constraints, backward compatibilty and easy coprocessor usage using an original strategy based on a hardware/software codesign methodolog

A Comprehensive Analysis of Literature Reported Mac and Phy Enhancements of Zigbee and its Alliances

Wireless communication is one of the most required technologies by the common man. The strength of this technology is rigorously progressing towards several novel directions in establishing personal wireless networks mounted over on low power consuming systems. The cutting-edge communication technologies like bluetooth, WIFI and ZigBee significantly play a prime role to cater the basic needs of any individual. ZigBee is one such evolutionary technology steadily getting its popularity in establishing personal wireless networks which is built on small and low-power digital radios. Zigbee defines the physical and MAC layers built on IEEE standard. This paper presents a comprehensive survey of literature reported MAC and PHY enhancements of ZigBee and its contemporary technologies with respect to performance, power consumption, scheduling, resource management and timing and address binding. The work also discusses on the areas of ZigBee MAC and PHY towards their design for specific applications

Dynamic partial reconfiguration for pipelined digital systems— A Case study using a color space conversion engine

In digital hardware design, reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) allow for a unique feature called partial reconfiguration PR). This refers to the reprogramming of a subset of the reconfigurable logic during active operation. PR allows multiple hardware blocks to be consolidated into a single partition, which can be reprogrammed at run-time as desired. This may reduce the logic circuit (and silicon area) requirements and greatly extend functionality. Furthermore, dynamic partial reconfiguration (DPR) refers to PR that does not halt the system during reprogramming. This allows for configuration to overlap with normal processing, potentially achieving better system performance than a static(halting) PR implementation. This work has investigated the advantages and trade-offs of DPR as applied to an existing color space conversion(CSC) engine provided by Hewlett-Packard (HP). Two versions were created: a single-pipeline engine, which can only overlap tasks in specific sequences; and a dual-pipeline engine, which can overlap any consecutive tasks. These were implemented in a Virtex-6 FPGA. Data communication occurs over the PCI Express (PCIe) interface. Test results show improvements in execution speed and resource utilization, though some are minor due to intrinsic characteristics of the CSC engine pipeline. The dual-pipeline version outperformed the single-pipeline in most test cases. Therefore, future work will focus on multiple-pipeline architectures

Towards a slime Mould-FPGA interface

© 2015, Korean Society of Medical and Biological Engineering and Springer. Purpose: The plasmodium of slime mouldPhysarum polycephalum: is a multinucleate single celled organism which behaves as a living amorphous unconventional computing substrate. As an excitable, memristive cell that typically assumes a branching or stellate morphology, slime mould is a unique model organism that shares many key properties of mammalian neurons. There are numerous studies that reveal the computing abilities of the plasmodium realized by the formation of tubular networks connecting points of interest. Recent research demonstrating typical responses in electrical behaviour of the plasmodium to certain chemical and physical stimuli has generated interest in creating an interface between.P. polycephalum: and digital logic, with the aim to perform computational tasks with the resulting device.Methods: Through a range of laboratory experiments, wemeasure plasmodial membrane potential via a non-invasive method and use this signal to interface the organism with a digital system.Results: This digital system was demonstrated to perform predefined basic arithmetic operations and is implemented in a field-programmable gate array (FPGA). These basic arithmetic operations, i.e. counting, addition, multiplying, use data that were derived by digital recognition of membrane potential oscillation and are used here to make basic hybrid biologicalartificial sensing devices.Conclusions: We present here a low-cost, energy efficient and highly adaptable platform for developing next-generation machine-organism interfaces. These results are therefore applicable to a wide range of biological/medical and computing/electronics fields