Исследование встроенных систем управления с программируемой логикой и структурно-пространственной адаптации с использованием имитационных моделей

Проведен анализ требований к встроенным системам управления с программируемой логикой (ВСУПЛ) и путей их реализации. Оценена скорость падения вероятности безотказной работы ВСУПЛ при накоплении отказов. Предложен метод имитационного моделирования, основанный на структурно-пространственной модели представления ВСУПЛ как инструмента оценки и выбора конфигураций отказоустойчивых структур. Приведен пример исследования структурно-пространственной адаптации для одноканальной, дублированной и трехканальной мажоритарной структуры

Dynamic Yield Analysis and Enhancement of FPGA Reconfigurable Memory Systems

This paper addresses the issues of field programmable gate arrays (FPGA) reconfigurable memory systems with faulty physical memory cells and proposes yield measurement techniques. Static yield (i.e., the yield which does not take into account the inherited redundancy utilization for repair) and dynamic yield (i.e., the yield which takes into account the inherited redundancy utilization for repair) of FPGA reconfigurable memory systems and their characteristics are extensively analyzed. Yield enhancement of conventional memory systems relies on additional redundancy, but FPGA reconfigurable memory systems have inherited redundancy and customizability. Thus, they can accommodate numerous target memory configurations, and redundant memory cells, if any, can be used as spares to enhance the dynamic yield of a target memory configuration. Three fundamental strategies are introduced and analyzed; i.e., redundant bit utilization, redundant word utilization, and a combination of both. Mathematical analysis of those techniques also has been conducted to study their effects on the yield. Selecting the most yield enhancing logical memory configuration which can accommodate a target memory requirement among the candidate configurations is referred to as optimal fitting. Optimal fitting algorithms for single configuration fitting, sequential reconfiguration system fitting, and concurrent reconfiguration system fitting are investigated based on the proposed yield analysis techniques

Evaluation of a Field Programmable Gate Array Circuit Reconfiguration System

This research implements a circuit reconfiguration system (CRS) to reconfigure a field programmable gate array (FPGA) in response to a faulty configurable logic block (CLB). It is assumed that the location of the fault is known and the CLB is moved according to one of four replacement methods: column left, column right, row up, and row down. Partial reconfiguration of the FPGA is done through the Joint Test Action Group (JTAG) port to produce the desired logic block movement. The time required to accomplish the reconfiguration is measured for each method in both clear and congested areas of the FPGA. The measured data indicate that there is no consistently better replacement method, regardless of the circuit congestion or location within the FPGA. Thus, given a specific location in the FPGA, there is no preferred replacement method that will result in the lowest reconfiguration time

Characterisation and mitigation of long-term degradation effects in programmable logic

Reliability has always been an issue in silicon device engineering, but until now it has been managed by the carefully tuned fabrication process. In the future the underlying physical limitations of silicon-based electronics, plus the practical challenges of manufacturing with such complexity at such a small scale, will lead to a crunch point where transistor-level reliability must be forfeited to continue achieving better productivity. Field-programmable gate arrays (FPGAs) are built on state-of-the-art silicon processes, but it has been recognised for some time that their distinctive characteristics put them in a favourable position over application-specific integrated circuits in the face of the reliability challenge. The literature shows how a regular structure, interchangeable resources and an ability to reconfigure can all be exploited to detect, locate, and overcome degradation and keep an FPGA application running. To fully exploit these characteristics, a better understanding is needed of the behavioural changes that are seen in the resources that make up an FPGA under ageing. Modelling is an attractive approach to this and in this thesis the causes and effects are explored of three important degradation mechanisms. All are shown to have an adverse affect on FPGA operation, but their characteristics show novel opportunities for ageing mitigation. Any modelling exercise is built on assumptions and so an empirical method is developed for investigating ageing on hardware with an accelerated-life test. Here, experiments show that timing degradation due to negative-bias temperature instability is the dominant process in the technology considered. Building on simulated and experimental results, this work also demonstrates a variety of methods for increasing the lifetime of FPGA lookup tables. The pre-emptive measure of wear-levelling is investigated in particular detail, and it is shown by experiment how di fferent reconfiguration algorithms can result in a significant reduction to the rate of degradation