1,412 research outputs found
VXA: A Virtual Architecture for Durable Compressed Archives
Data compression algorithms change frequently, and obsolete decoders do not
always run on new hardware and operating systems, threatening the long-term
usability of content archived using those algorithms. Re-encoding content into
new formats is cumbersome, and highly undesirable when lossy compression is
involved. Processor architectures, in contrast, have remained comparatively
stable over recent decades. VXA, an archival storage system designed around
this observation, archives executable decoders along with the encoded content
it stores. VXA decoders run in a specialized virtual machine that implements an
OS-independent execution environment based on the standard x86 architecture.
The VXA virtual machine strictly limits access to host system services, making
decoders safe to run even if an archive contains malicious code. VXA's adoption
of a "native" processor architecture instead of type-safe language technology
allows reuse of existing "hand-optimized" decoders in C and assembly language,
and permits decoders access to performance-enhancing architecture features such
as vector processing instructions. The performance cost of VXA's virtualization
is typically less than 15% compared with the same decoders running natively.
The storage cost of archived decoders, typically 30-130KB each, can be
amortized across many archived files sharing the same compression method.Comment: 14 pages, 7 figures, 2 table
Digital Photo Frame
With the advancement in semiconductor technology, scope for development of embedded systems has increased manifolds. New processors with improved computing capabilities and low power consumption have further accelerated the developments in embedded domain. Consumers are looking for affordable multimedia devices with high performance and durability making embedded developers to think creatively and use all resources at hand to meet the desired user specifications. This is one such attempt by designing a digital photo frame with 5 inch LCD display intended to display high quality BMP images. Small Size and low cost of development can prove to be very useful in the success of the device as a day to day consumer electronics product. Powerful computing capabilities of ARM processor when duly utilised can produce very elegant results
Compiler optimization and ordering effects on VLIW code compression
Code size has always been an important issue for all embedded applications as well as larger systems. Code compression techniques have been devised as a way of battling bloated code; however, the impact of VLIW compiler methods and outputs on these compression schemes has not been thoroughly investigated. This paper describes the application of single- and multipleinstruction dictionary methods for code compression to decrease overall code size for the TI TMS320C6xxx DSP family. The compression scheme is applied to benchmarks taken from the Mediabench benchmark suite built with differing compiler optimization parameters. In the single instruction encoding scheme, it was found that compression ratios were not a useful indicator of the best overall code size – the best results (smallest overall code size) were obtained when the compression scheme was applied to sizeoptimized code. In the multiple instruction encoding scheme, changing parallel instruction order was found to only slightly improve compression in unoptimized code and does not affect the code compression when it is applied to builds already optimized for size
Trends in hardware architecture for mobile devices
In the last ten years, two main factors have fueled the steady growth in sales
of mobile computing and communication devices: a) the reduction of the
footprint of the devices themselves, such as cellular handsets and small
computers; and b) the success in developing low-power hardware which allows
the devices to operate autonomously for hours or even days. In this review, I
show that the first generation of mobile devices was DSP centric – that is,
its architecture was based in fast processing of digitized signals using low-
power, yet numerically powerful DSPs. However, the next generation of mobile
devices will be built around DSPs and low power microprocessor cores for
general processing applications. Mobile devices will become data-centric. The
main challenge for designers of such hybrid architectures is to increase the
computational performance of the computing unit, while keeping power constant,
or even reducing it. This report shows that low-power mobile hardware
architectures design goes hand in hand with advances in compiling techniques.
We look at the synergy between hardware and software, and show that a good
balance between both can lead to innovative lowpower processor architectures
Design of Audio Player and Recorder on STM 32F4 Discovery Board
With the advancement in semiconductor technology, scope for development of embedded systems has increased manifolds. New processors with improved computing capabilities and low power consumption have further accelerated the developments in embedded domain. Consumers are looking for affordable multimedia devices with high performance and durability making embedded developers to think creatively and use all resources at hand to meet the desired user specifications. This is one such attempt by designing an Audio Player and Recorder to play the wave audio files from a USB flash drive and recording the audio in USB flash drive in the same format. In this application MEMS microphone is used for recording the audio dat
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