Design of Dual and Swing Restored Complementary Pass Transistor Logic for Low Power Ripple Carry Array Multiplier

In a conventional array multiplier many number of CMOS structures are used in designing. Here this paper presents a multiplier that uses an alternative internal logic structure in designing. The project uses pass transistors logic designs leading to reduction of power usage

High speed multiplier design using Decomposition Logic

The multiplier forms the core of a Digital Signal Processor and is a major source of power dissipation. Often, the multiplier forms the limiting factor for the maximum speed of operation of a Digital Signal Processor. Due to continuing integrating intensity and the growing needs of portable devices, low-power, high-performance design is of prime importance. A new technique of implementing a multiplier circuit using Decomposition Logic is proposed here which improves speed with very little increase in power dissipation when compared to tree structured Dadda multipliers. Tanner EDA was used for simulation in the TSMC 180nm technology

Review On High Performance Quaternary Arithmetic and Logical Unit in Standard CMOS

Arithmetic circuits play an important role in computational circuits. Multiple Valued Logic (MVL) provides higher density per integrated circuit area compared to traditional two valued binary logic. Quaternary (Four-valued) logic also provides easy interfacing to binary logic because radix 4(22) allows for the use of simple encoding/decoding circuits. The functional completeness is proved by a set of fundamental quaternary cells and the collection of cells based on the Supplementary Symmetrical Logic Circuit Structure (SUSLOC). Cells are designed, simulated, and used to build several quaternary fixed-point arithmetic circuits such as adders, multipliers etc. These SUSLOC circuit cells are validated using SPICE models and the arithmetic architectures are validated using System Verilog models for functional correctness. Quaternary (radix-4) dual operand encoding principles are applied to optimize power and performance of adder circuits using standard CMOS gates technologies

Cost effectiveness filter design for low-latency audio analogue to digital converter (Σ-ΔADC)

The current technical challenge posed in professional audio industry is to have a small size portable device, which can support real-time interactive applications. Σ-Δ Modulation based audio system becomes the mainstream due to the higher resolution and fewer auxiliary circuits. However, extremely high sampling frequency brings severe challenges to its decimation or interpolation filter design and performance. The current optimal filter design parameter calculation methods have room for improvement, such as complex calculations and results need further rounding. Therefore, Author proposed a new optimal decimation or interpolation rate selection approach converts the optimization problem to factorization and permutation problem which improves the effciency significantly and provides directly usable integer solutions. Furthermore, due to the lack of theoretical relationship between latency of filter and multi-stage design parameters a latency estimation equation is derived by author. The analysis of this equation shows that optimal computational cost design and optimal latency design have contradictory requirements. Hence, the optimization of filter design parameter is added to optimize the other costs as much as possible. Thus, author proposed a new numeric optimization based method to design the cost effcient low-latency multi-stage multi-rate Filter. This approach further reduces the costs of the filter on the basis of the previous optimal design. At last, a MATLAB GUI based filter design and evaluation framework has been established which can help user to search the optimal design parameters and design optimal filters with different filter types