9 research outputs found
Binary Weighted Memristive Analog Deep Neural Network for Near-Sensor Edge Processing
The memristive crossbar aims to implement analog weighted neural network,
however, the realistic implementation of such crossbar arrays is not possible
due to limited switching states of memristive devices. In this work, we propose
the design of an analog deep neural network with binary weight update through
backpropagation algorithm using binary state memristive devices. We show that
such networks can be successfully used for image processing task and has the
advantage of lower power consumption and small on-chip area in comparison with
digital counterparts. The proposed network was benchmarked for MNIST
handwritten digits recognition achieving an accuracy of approximately 90%
In-situ Stochastic Training of MTJ Crossbar based Neural Networks
Owing to high device density, scalability and non-volatility, Magnetic Tunnel
Junction-based crossbars have garnered significant interest for implementing
the weights of an artificial neural network. The existence of only two stable
states in MTJs implies a high overhead of obtaining optimal binary weights in
software. We illustrate that the inherent parallelism in the crossbar structure
makes it highly appropriate for in-situ training, wherein the network is taught
directly on the hardware. It leads to significantly smaller training overhead
as the training time is independent of the size of the network, while also
circumventing the effects of alternate current paths in the crossbar and
accounting for manufacturing variations in the device. We show how the
stochastic switching characteristics of MTJs can be leveraged to perform
probabilistic weight updates using the gradient descent algorithm. We describe
how the update operations can be performed on crossbars both with and without
access transistors and perform simulations on them to demonstrate the
effectiveness of our techniques. The results reveal that stochastically trained
MTJ-crossbar NNs achieve a classification accuracy nearly same as that of
real-valued-weight networks trained in software and exhibit immunity to device
variations.Comment: Accepted for poster presentation in the 2018 ACM/IEEE International
Symposium on Low Power Electronics and Design (ISLPED
Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition
A neuromorphic chip that combines CMOS analog spiking neurons and memristive
synapses offers a promising solution to brain-inspired computing, as it can
provide massive neural network parallelism and density. Previous hybrid analog
CMOS-memristor approaches required extensive CMOS circuitry for training, and
thus eliminated most of the density advantages gained by the adoption of
memristor synapses. Further, they used different waveforms for pre and
post-synaptic spikes that added undesirable circuit overhead. Here we describe
a hardware architecture that can feature a large number of memristor synapses
to learn real-world patterns. We present a versatile CMOS neuron that combines
integrate-and-fire behavior, drives passive memristors and implements
competitive learning in a compact circuit module, and enables in-situ
plasticity in the memristor synapses. We demonstrate handwritten-digits
recognition using the proposed architecture using transistor-level circuit
simulations. As the described neuromorphic architecture is homogeneous, it
realizes a fundamental building block for large-scale energy-efficient
brain-inspired silicon chips that could lead to next-generation cognitive
computing.Comment: This is a preprint of an article accepted for publication in IEEE
Journal on Emerging and Selected Topics in Circuits and Systems, vol 5, no.
2, June 201
Neuro-memristive Circuits for Edge Computing: A review
The volume, veracity, variability, and velocity of data produced from the
ever-increasing network of sensors connected to Internet pose challenges for
power management, scalability, and sustainability of cloud computing
infrastructure. Increasing the data processing capability of edge computing
devices at lower power requirements can reduce several overheads for cloud
computing solutions. This paper provides the review of neuromorphic
CMOS-memristive architectures that can be integrated into edge computing
devices. We discuss why the neuromorphic architectures are useful for edge
devices and show the advantages, drawbacks and open problems in the field of
neuro-memristive circuits for edge computing
Memristors
This Edited Volume Memristors - Circuits and Applications of Memristor Devices is a collection of reviewed and relevant research chapters, offering a comprehensive overview of recent developments in the field of Engineering. The book comprises single chapters authored by various researchers and edited by an expert active in the physical sciences, engineering, and technology research areas. All chapters are complete in itself but united under a common research study topic. This publication aims at providing a thorough overview of the latest research efforts by international authors on physical sciences, engineering, and technology,and open new possible research paths for further novel developments