10,584 research outputs found
Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System
Emulating spiking neural networks on analog neuromorphic hardware offers
several advantages over simulating them on conventional computers, particularly
in terms of speed and energy consumption. However, this usually comes at the
cost of reduced control over the dynamics of the emulated networks. In this
paper, we demonstrate how iterative training of a hardware-emulated network can
compensate for anomalies induced by the analog substrate. We first convert a
deep neural network trained in software to a spiking network on the BrainScaleS
wafer-scale neuromorphic system, thereby enabling an acceleration factor of 10
000 compared to the biological time domain. This mapping is followed by the
in-the-loop training, where in each training step, the network activity is
first recorded in hardware and then used to compute the parameter updates in
software via backpropagation. An essential finding is that the parameter
updates do not have to be precise, but only need to approximately follow the
correct gradient, which simplifies the computation of updates. Using this
approach, after only several tens of iterations, the spiking network shows an
accuracy close to the ideal software-emulated prototype. The presented
techniques show that deep spiking networks emulated on analog neuromorphic
devices can attain good computational performance despite the inherent
variations of the analog substrate.Comment: 8 pages, 10 figures, submitted to IJCNN 201
Six networks on a universal neuromorphic computing substrate
In this study, we present a highly configurable neuromorphic computing substrate and use it for emulating several types of neural networks. At the heart of this system lies a mixed-signal chip, with analog implementations of neurons and synapses and digital transmission of action potentials. Major advantages of this emulation device, which has been explicitly designed as a universal neural network emulator, are its inherent parallelism and high acceleration factor compared to conventional computers. Its configurability allows the realization of almost arbitrary network topologies and the use of widely varied neuronal and synaptic parameters. Fixed-pattern noise inherent to analog circuitry is reduced by calibration routines. An integrated development environment allows neuroscientists to operate the device without any prior knowledge of neuromorphic circuit design. As a showcase for the capabilities of the system, we describe the successful emulation of six different neural networks which cover a broad spectrum of both structure and functionality
Demonstrating Advantages of Neuromorphic Computation: A Pilot Study
Neuromorphic devices represent an attempt to mimic aspects of the brain's
architecture and dynamics with the aim of replicating its hallmark functional
capabilities in terms of computational power, robust learning and energy
efficiency. We employ a single-chip prototype of the BrainScaleS 2 neuromorphic
system to implement a proof-of-concept demonstration of reward-modulated
spike-timing-dependent plasticity in a spiking network that learns to play the
Pong video game by smooth pursuit. This system combines an electronic
mixed-signal substrate for emulating neuron and synapse dynamics with an
embedded digital processor for on-chip learning, which in this work also serves
to simulate the virtual environment and learning agent. The analog emulation of
neuronal membrane dynamics enables a 1000-fold acceleration with respect to
biological real-time, with the entire chip operating on a power budget of 57mW.
Compared to an equivalent simulation using state-of-the-art software, the
on-chip emulation is at least one order of magnitude faster and three orders of
magnitude more energy-efficient. We demonstrate how on-chip learning can
mitigate the effects of fixed-pattern noise, which is unavoidable in analog
substrates, while making use of temporal variability for action exploration.
Learning compensates imperfections of the physical substrate, as manifested in
neuronal parameter variability, by adapting synaptic weights to match
respective excitability of individual neurons.Comment: Added measurements with noise in NEST simulation, add notice about
journal publication. Frontiers in Neuromorphic Engineering (2019
Versatile emulation of spiking neural networks on an accelerated neuromorphic substrate
We present first experimental results on the novel BrainScaleS-2 neuromorphic
architecture based on an analog neuro-synaptic core and augmented by embedded
microprocessors for complex plasticity and experiment control. The high
acceleration factor of 1000 compared to biological dynamics enables the
execution of computationally expensive tasks, by allowing the fast emulation of
long-duration experiments or rapid iteration over many consecutive trials. The
flexibility of our architecture is demonstrated in a suite of five distinct
experiments, which emphasize different aspects of the BrainScaleS-2 system
A Scalable Approach to Modeling on Accelerated Neuromorphic Hardware.
Neuromorphic systems open up opportunities to enlarge the explorative space for computational research. However, it is often challenging to unite efficiency and usability. This work presents the software aspects of this endeavor for the BrainScaleS-2 system, a hybrid accelerated neuromorphic hardware architecture based on physical modeling. We introduce key aspects of the BrainScaleS-2 Operating System: experiment workflow, API layering, software design, and platform operation. We present use cases to discuss and derive requirements for the software and showcase the implementation. The focus lies on novel system and software features such as multi-compartmental neurons, fast re-configuration for hardware-in-the-loop training, applications for the embedded processors, the non-spiking operation mode, interactive platform access, and sustainable hardware/software co-development. Finally, we discuss further developments in terms of hardware scale-up, system usability, and efficiency
Hybrid Linux System Modeling with Mixed-Level Simulation
Dissertação de mestrado integrado em Engenharia Electrónica Industrial e ComputadoresWe live in a world where the need for computer-based systems with better performances
is growing fast, and part of these systems are embedded systems. This
kind of systems are everywhere around us, and we use them everyday even without
noticing. Nevertheless, there are issues related to embedded systems in what comes
to real-time requirements, because the failure of such systems can be harmful
to the user or its environment.
For this reason, a common technique to meet real-time requirements in difficult
scenarios is accelerating software applications by using parallelization techniques
and dedicated hardware components. This dissertations’ goal is to adopt a methodology
of hardware-software co-design aided by co-simulation, making the design
flow more efficient and reliable. An isolated validation does not guarantee integral
system functionality, but the use of an integrated co-simulation environment
allows detecting system problems before moving to the physical implementation.
In this dissertation, an integrated co-simulation environment will be developed,
using the Quick EMUlator (QEMU) as a tool for emulating embedded software
platforms in a Linux-based environment. A SystemVerilog Direct Programming
Interface (DPI) Library was developed in order to allow SystemVerilog simulators
that support DPI to perform co-simulation with QEMU. A library for DLL
blocks was also developed in order to allow PSIMR to communicate with QEMU.
Together with QEMU, these libraries open up the possibility to co-simulate several
parts of a system that includes power electronics and hardware acceleration
together with an emulated embedded platform.
In order to validate the functionality of the developed co-simulation environment,
a demonstration application scenario was developed following a design flow that
takes advantage of the mentioned simulation environment capabilities.Vivemos num mundo em que a procura por sistemas computer-based com desempenhos
cada vez melhores domina o mercado. Estamos rodeados por este tipo de
sistemas, usando-os todos os dias sem nos apercebermos disso, sendo grande parte
deles sistemas embebidos. Ainda assim, existem problemas relacionados com os
sistemas embebidos no que toca aos requisitos de tempo-real, porque uma falha
destes sistemas pode ser perigosa para o utilizador ou o ambiente que o rodeia.
Devido a isto, uma técnica comum para se conseguir cumprir os requisitos de
tempo-real em aplicações críticas é a aceleração de aplicações de software, utilizando
técnicas de paralelização e o uso de componentes de hardware dedicados.
O objetivo desta dissertação é adotar uma metodologia de co-design de hardwaresoftware
apoiada em co-simulação, tornando o design flow mais eficiente e fiável.
Uma validação isolada não garante a funcionalidade do sistema completo, mas a
utilização de um ambiente de co-simulação permite detetar problemas no sistema
antes deste ser implementado na plataforma alvo.
Nesta dissertação será desenvolvido um ambiente de co-simulação usando o QEMU
como emulador para as plataformas de software "embebido" baseadas em Linux.
Uma biblioteca para SystemVerilog DPI foi desenvolvida, que permite a co-simulação
entre o QEMU e simuladores de Register-Transfer Level (RTL) que suportem SystemVerilog.
Foi também desenvolvida uma biblioteca para os blocos Dynamic Link
Library (DLL) do PSIMR , de modo a permitir a ligação ao QEMU. Em conjunto,
as bibliotecas desenvolvidas permitem a co-simulação de diversas partes do sistema,
nomeadamente do hardware de eletrónica de potência e dos aceleradores de
hardware, juntamente com a plataforma embebida emulada no QEMU.Para validar as funcionalidades do ambiente de co-simulação desenvolvido, foi explorado
um cenário de aplicação que tem por base esse mesmo ambiente
Roadmap on semiconductor-cell biointerfaces.
This roadmap outlines the role semiconductor-based materials play in understanding the complex biophysical dynamics at multiple length scales, as well as the design and implementation of next-generation electronic, optoelectronic, and mechanical devices for biointerfaces. The roadmap emphasizes the advantages of semiconductor building blocks in interfacing, monitoring, and manipulating the activity of biological components, and discusses the possibility of using active semiconductor-cell interfaces for discovering new signaling processes in the biological world
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