Clock Around Embedded Systems and Reconfigurable Systems

The influence of Von Neumann computer model [4] and the second EDVAC computer built by the Moore School deeply influenced the last 50 years of computer sciences and embedded systems. The FPGA (Field Programmable Gate) technology brings another possibility to the field as introduced the reconfigurable computing concept. The paper gives one possible view of this research field

Perbandingan Bahasa Pendeskripsian Perangkat Keras SystemC Terhadap Verilog dengan Studi Kasus Single Purpose untuk Least Common Multiple

ABSTRAKSI: Pada tahapan desain dari perancangan embedded system menggunakan hardware description language (HDL), kemungkinan ada perbedaan karakteristik untuk penggunaan HDL berbeda. Oleh karena itu, perlu dilakukan pembandingan karakteristik antara HDL berbeda, dalam tugas akhir ini yaitu antara SystemC dan Verilog. Perbandingan dilakukan pada implementasi dari sebuah single-purpose processor dengan fungsionalitas least common multiple (LCM), dengan parameter yang diperbandingkan yaitu latency, memory consumption, runtime delay, dan harddisk allocation. Prosesnya meliputi pemodelan LCM dengan state-machine modeling, pengoptimasian (jika perlu), pembangunan blok diagram, kemudian diimplementasikan ke dalam bahasa SystemC dan Verilog, dan berakhir dengan pengukuran masing-masing parameter yang diperbandingkan. Pada penelitian ini didapati sejumlah kelebihan dan kekurangan dari masingmasing bahasa seperti kemampuan Verilog terhadap pendefinisian clock timing pada kendali yang lebih baik dibandingkan dengan SystemC, dan kemampuan SystemC yang lebih baik dalam hal fleksibilitas.Kata Kunci : systemc, LCM, verilog, single-purpose processorABSTRACT: In designing phase of embedded system designing using hardware description language (HDL), some characteristics may differ due to using different HDL. That is why it is necessary needed to compare those characteristics between two different HDL, which is, in this final assignment, between SystemC and Verilog. The comparison is done in an implementation of a single-purpose processor with least common multiple (LCM) functionality, in which, compared parameters are latency, memory consumption, runtime delay, and harddisk allocation. There are some steps which should be done, LCM modeling using state-machine modeling, optimation (only if needed), creating diagram block, and implementing it into SystemC and Verilog language, and finally, calculating each compared parameter. In this research, we found several strengths and weaknesses, such as Verilog’s ability in defining clock timing for controller is better than SystemC’s one, and vice versa, SystemC’s ability is better in flexibility term than Verilog’s one.Keyword: systemc, LCM, verilog, single-purpose processo

UAV payload and mission control hardware/software architecture

This paper presents an embedded hardware/software architecture specially designed to be applied on mini/micro Unmanned Aerial Vehicles (UAV). An UAV is low-cost non-piloted airplane designed to operate in D-cube (Dangerous-Dirty-Dull) situations [8]. Many types of UAVs exist today; however with the advent of UAV's civil applications, the class of mini/micro UAVs is emerging as a valid option in a commercial scenario. This type of UAV shares limitations with most computer embedded systems: limited space, limited power resources, increasing computation requirements, complexity of the applications, time to market requirements, etc. UAVs are automatically piloted by an embedded system named “Flight Control System”. Many of those systems are commercially available today, however no commercial system exists nowadays that provides support to the actual mission that the UAV should perform. This paper introduces a hardware/software architecture specially designed to operate as a flexible payload and mission controller in a mini/micro UAV. Given that the missions UAVs can carry on justify their existence, we believe that specific payload and mission controller s for UAV should be developed. Our architectonic proposal for them orbits around four key elements: a LAN based distributed and scalable hardware architecture, a service/subscription based software architecture and an abstraction communication layer.Peer Reviewe