Formation & characterization of p/n shallow junctions in sub-micron MOSFETs

The formation of shallow junctions in the source and drain regions is a major challenge to the continued success of scaling of complementary metal oxide semiconductors (CMOS) circuits. The formation of these device structures requires low-energy ion implantation and rapid thermal annealing (RTA). One of the processes which has been shown to be advantageous is spike annealing, with fast ramping and short dwell time at maximum temperature. This work is a study of the effects of implant energy, implant dose and annealing cycles on the reverse-bias leakage current in the diode junction. The reversebias leakage is the study of junction quality. Low leakage is ideal, but for some experimental processes, leakage is found to be high. Experiments have been performed on p/n diode samples, which were annealed by various methods. The methods of annealing include spike anneals by (a) arc lamp, (b) incandescent lamp and (c) flash annealing. Implant conditions were typically ultra-low energy B implants (0.5 keV & 5 keV), which also included Ge pre-amorphization implants (PAI). A general observation is that the junctions with least leakage are obtained for B implants without PAI. When the PAI step is included, the best shallow junctions are obtained if the PAI depth is greater than the junction depth, because of the damage produced by PAI. Flash annealing of B implants with PAI showed very high leakage, when compared to conventional spike annealing, apparently because it does not sufficiently anneal out the implant damage

Formation and characterization of n/p shallow junctions in sub-micron MOSFETs

Semiconductors are the burgeoning industries in today\u27s information age. Silicon based microelectronic devices are shrinking day-by-day in accord with the scaling dimensions reported by the International Technology Roadmap for Semiconductors (ITRS). There have been many semiconductor models and simulation programs constantly keeping pace with the continuously evolving scaling dimensions, process technology, performance and cost. Electrical characterization plays a vital role in determining the electrical properties of materials and device structures. Silicon based Metal Oxide Semiconductor Field Effect Transistor (MOSFET) forms the basis of Complimentary Metal Oxide Semiconductor (CMOS) circuits. Today\u27s aggressive scaling approaches in silicon Integrated Circuit (IC) technology require ultra shallow junctions in MOSFETs. The objective of this thesis is to study the leakage current in n/p shallow junctions and to correlate them with process steps required for the formation of shallow junctions. The leakage current measurements were performed by utilizing three-point probe method, which is one of the popular techniques used in the semiconductor industry. Apart from n/p shallow junctions, experiments have been performed on p/n shallow junctions. Finally, comparison of the leakage current measurements has been made. The comparison takes into account the implant variables and post-implant annealing steps that have been deployed in the fabrication of shallow junctions

Defect Engineering in the formation of Ultra-shallow junctions for advanced nano-metal-oxide-semiconductor technology

Ph.DDOCTOR OF PHILOSOPH

Optimisation du procédé de réalisation pour l'intégration séquentielle 3D des transistors CMOS FDSOI

L activation à basse température est prometteuse pour l intégration 3D séquentielle où lebudget thermique du transistor supérieur est limité (<650 C) pour ne pas dégrader letransistor inférieur, mais aussi dans le cas d une intégration planaire afin d atteindre des EOTultra fines et de contrôler le travail de sortie de la grille sans recourir à une intégration de type gate-last . Dans ce travail, l activation par recroissance en phase solide (SPER) a étéétudiée afin de réduire le budget thermique de l activation des dopants.L activation à basse température présente plusieurs inconvénients. Les travauxprécédents montrent que les fuites de jonctions sont plus importantes dans ces dispositifs.Ensuite, des fortes désactivations de dopants ont été observées. Troisièmement, la faiblediffusion des dopants rend difficile la connexion des jonctions source et drain avec le canal.Dans ce travail, il est montré que dans un transistor FDSOI, l augmentation des fuites dejonctions et la désactivation du Bore peuvent être évités grâce à la présence de l oxyde enterré.De plus les conditions d implantation ont été optimisées et les transistors activés à650 C atteignent les performances des transistors de référence.Low temperature (LT) process is gaining interest in the frame of 3D sequentialintegration where limited thermal budget (<650 C) is needed for top FET to preserve bottomFET from any degradation and also in the standard planar integration for achieving ultra-thinEOT and work function control with high-k metal gate without gate-last integration scheme.In this work, LT Solid Phase Epitaxial Regrowth (SPER) has been investigated for reducingthe most critical thermal budget which is dopant activation.From previous works, LT activated devices face several challenges: First, higher junctionleakage limits their application to high performance devices. Secondly, strong deactivation ofthe metastable activated dopants was observed with post anneals. Thirdly, the dopant weakdiffusion makes it difficult to connect the channel with S/D.In this work, it is shown that the use of FDSOI enables to overcome junction leakage andBoron deactivation issues thanks to the defect cutting off and sinking effect of buried oxide.As a consequence, dopant deactivation in FDSOI devices is no longer an issue. Finally,implants conditions of LT transistors have been optimized to reach similar performance thanits standard high temperature counterparts.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Fabrication and characterization of nanocrystalline silicon LEDs : a study of the influence of annealing

This thesis describes the fabrication of a set of bright, visible light-emitting silicon LEDs. These devices were fabricated in-house at the University of Saskatchewan using a custom plasma ion implantation tool, an annealing furnace, and a physical vapour deposition system. A high-fluence (F = 4 × 1015 cm^−2) implantation of molecular hydrogen ions extracted from an RF inductively coupled plasma at an energy of 5 keV was used to create a heavily damaged region in the silicon centered approximately 40 nm below the silicon surface with a width of approximately 56 nm. A matrix of annealing (e.g. thermal processing) processes at 400 ºC and 700 ºC and different durations (30 minutes and 2 hours) as well as an aluminum gettering procedure were tested with the goal of increasing the output electroluminescence intensity. Current-voltage characterization was used to extract information about the defect-rich nanocrystalline, light-emitting layer as well as the Schottky barrier height. This enabled comparison of these new devices with previous silicon LEDs based on porous silicon and other approaches. The processes which were used to fabricate these devices are compatible with standard CMOS processing techniques and could provide one solution to the problem of optical interconnect on multi-core chips. The scientific significance of this work is the demonstration of bright, visible light emission at mean photon energies ∼1.84 eV corresponding to a photon wavelength of λ ≈ 675 nm. This is remarkable given that ordinary crystalline silicon is an indirect bandgap material with a bandgap energy of 1.1 eV, in which band-to-band radiative recombination is forbidden by momentum conservation. The devices fabricated in this thesis have light emission properties similar to previous silicon LEDs based on nanocrystalline or nanoporous silicon. They have the advantage of being easily electrically driven. The nanocrystalline region which is the source of the light emission was nucleated from the ion-implanted layer below the surface of the silicon. This makes these devices mechanically robust and insensitive to environmental conditions. The engineering significance of this work is the production of CMOS compatible light emitters. This study demonstrated increased light emission efficiency at higher annealing temperatures which is likely due to enhanced diffusion and nucleation of silicon nanocrystals in the ion-implant damaged layer

Boron and phosphorous implantation into (100) germanium : modeling and investigation of dopant annealing behavior

Germanium is increasingly being considered at this time for future silicon compatible optoelectronic and complementary metal oxide semiconductor (CMOS) device application. Germanium implantation will be a critical process for future device fabrication. However, critical properties like Pearson parameters and dopant activation temperatures are not well established. In this study, boron and phosphorus were implanted into (100) germanium with energies ranging from 20 to 320 keV and doses of 5 x 1013 to 5 x 1016 cm-2. The behavior of the boron and phosphorus before and after annealing for 3 hours at 400, 600 or 800°C in ultra high purity nitrogen were characterized using secondary ion mass spectrometry (SIMS), spreading resistance profiling (SRP) measurements, Hall Effect measurement, X-ray diffraction (XRD) measurement, and Rutherford backscattering spectrometry (RB S). A predictive model for the implanted dopant distribution\u27s dependence on energy was developed using the experimentally determined implant moments combined with Pearson distributions and the post-annealing electrical, structural and diffusion behavior was characterized. Results from numeric simulation and analytic calculations using Lindard-Scharff-Schiott (LSS) theory are presented to offer insight into the physics of the pre-annealed implanted dopant distributions

Engineering order-disorder transitions at the surface of topological insulators to manipulate electronic transport

The theoretical discovery and experimental realisation of topological insulators, a new state of matter, has brought enormous research interest in the field of condensed matter physics. The novel and fascinating phenomenon in topological insulators (TIs) is the existence of gapless surface states (or edge states) while the bulk interior has an energy gap. These states are intriguing because they enable the transport of charges with no backscattering, which means less heat generation than ordinary conductors. The unique transport in TIs arises because of the spin-momentum locking of the surface states. Thus, the promising properties of the TIs have the potential for applications in low-energy quantum electronics and spintronics. The research is motivated by a recent series of theories discussing the existence of amorphous topological materials and exploring the practical applications of the TIs in the semiconductor industry. The current research has extensively studied the feasibility of ion-beam patterning of a 3D strong topological insulator Sb2Te3. Subsequently, both in experiment and theory, this thesis proposes a novel method of engineering topological surface and edge states based on controlling the topological phase transition of Sb2Te3 with a focused ion-beam

Characterisation of nickel germanide formed on amorphous and crystalline germanium

Germanium offers unique properties as a semiconductor materials for complementary metal&amp;ndash;oxide&amp;ndash;semiconductor (CMOS) devices with nearly four times the hole mobility and two times the electron mobility of silicon resulting in higher currents. However, two essential requirements in the application of Ge for CMOS technology are the formation of shallow junctions and the formation of ohmic metal contacts with low resistance. High diffusivity of dopants in crystalline germanium is a problem when forming shallow junctions. However, amorphisation of crystalline germanium where dopant implants are to occur leads to shallow junctions. In this work both amorphous and crystalline germanium (a-Ge and c-Ge) are investigated. Nickel germanide (NiGe) formed on a-Ge and c-Ge is investigated for material and electrical properties. NiGe has been reported as a suitable germanide for low resistance ohmic contacts on c-Ge. The crystal quality of films formed is poorer for the germanides formed on a-Ge but there is only a slight increase in sheet resistance. The grains of NiGe formed on a-Ge show a growth that is hexagonal like, extending into the substrate further than germanides grains formed on crystalline germanium. The NiGe formed on c-Ge has a much more uniform thickness and uniform grain size and shape. Thin films of nickel germanide conveniently form at the relatively low temperature of 300C in a matter of minutes and at even lower temperatures over a longer time. This thesis reports on the formation of NiGe on c-Ge substrates at low temperatures (less than 300&amp;deg;C). Ni films deposited on Ge substrates formed NiGe by heating the samples in an atmosphere VI nearly void of oxygen. Ni films of thickness 50 to 400 nm were deposited on c-Ge and heat treatments undertaken on samples for time durations of 5 minutes to 12 hours at different temperatures. It was found that thickness of 25nm to 100 nm was not a significant factor and that NiGe formed in a few minutes on c-Ge for this thickness of Ni heated at 300&amp;deg;C. The temperature of formation for 400 nm reacting with germanium was longer. For all thickness of Ni, long durations were required for the lowest temperature of formation which were between 225&amp;deg;C and less than 300&amp;deg;C. The sheet resistances of NiGe on a-Ge and c-Ge are suitably low for use in CMOS technology. Metal contacts to NiGe were investigated and low resistance contacst were obtained. The contacts to c-Ge were significantly better. Improvements in processing is required for suitably low resistance contacts to be obtained for metal to NiGe formed on aGe, but results obtained here are promising and further investigation is warranted. NiGe on a-Ge shows poorer grain crystal quality and improvements in this are likely to lead to contacts with lower specific contact resistivity