New constructions of WOM codes using the Wozencraft ensemble

In this paper we give several new constructions of WOM codes. The novelty in our constructions is the use of the so called Wozencraft ensemble of linear codes. Specifically, we obtain the following results. We give an explicit construction of a two-write Write-Once-Memory (WOM for short) code that approaches capacity, over the binary alphabet. More formally, for every \epsilon>0, 0<p<1 and n =(1/\epsilon)^{O(1/p\epsilon)} we give a construction of a two-write WOM code of length n and capacity H(p)+1-p-\epsilon. Since the capacity of a two-write WOM code is max_p (H(p)+1-p), we get a code that is \epsilon-close to capacity. Furthermore, encoding and decoding can be done in time O(n^2.poly(log n)) and time O(n.poly(log n)), respectively, and in logarithmic space. We obtain a new encoding scheme for 3-write WOM codes over the binary alphabet. Our scheme achieves rate 1.809-\epsilon, when the block length is exp(1/\epsilon). This gives a better rate than what could be achieved using previous techniques. We highlight a connection to linear seeded extractors for bit-fixing sources. In particular we show that obtaining such an extractor with seed length O(log n) can lead to improved parameters for 2-write WOM codes. We then give an application of existing constructions of extractors to the problem of designing encoding schemes for memory with defects.Comment: 19 page

Trajectory Codes for Flash Memory

Flash memory is well-known for its inherent asymmetry: the flash-cell charge levels are easy to increase but are hard to decrease. In a general rewriting model, the stored data changes its value with certain patterns. The patterns of data updates are determined by the data structure and the application, and are independent of the constraints imposed by the storage medium. Thus, an appropriate coding scheme is needed so that the data changes can be updated and stored efficiently under the storage-medium's constraints. In this paper, we define the general rewriting problem using a graph model. It extends many known rewriting models such as floating codes, WOM codes, buffer codes, etc. We present a new rewriting scheme for flash memories, called the trajectory code, for rewriting the stored data as many times as possible without block erasures. We prove that the trajectory code is asymptotically optimal in a wide range of scenarios. We also present randomized rewriting codes optimized for expected performance (given arbitrary rewriting sequences). Our rewriting codes are shown to be asymptotically optimal.Comment: Submitted to IEEE Trans. on Inform. Theor

Using Short Synchronous WOM Codes to Make WOM Codes Decodable

In the framework of write-once memory (WOM) codes, it is important to distinguish between codes that can be decoded directly and those that require that the decoder knows the current generation to successfully decode the state of the memory. A widely used approach to construct WOM codes is to design first nondecodable codes that approach the boundaries of the capacity region, and then make them decodable by appending additional cells that store the current generation, at an expense of a rate loss. In this paper, we propose an alternative method to make nondecodable WOM codes decodable by appending cells that also store some additional data. The key idea is to append to the original (nondecodable) code a short synchronous WOM code and write generations of the original code and of the synchronous code simultaneously. We consider both the binary and the nonbinary case. Furthermore, we propose a construction of synchronous WOM codes, which are then used to make nondecodable codes decodable. For short-to-moderate block lengths, the proposed method significantly reduces the rate loss as compared to the standard method.Comment: To appear in IEEE Transactions on Communications. The material in this paper was presented in part at the 2012 IEEE International Symposium on Information Theory, Cambridge, MA, July 201

플래시 메모리를 위한 양방향 비대칭 오류 정정 부호 및 간섭 완화 기법

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 이정우.Recently, NAND multi-level cell (MLC) flash memories are now widely used due to low cost and high capacity. However, when the number of cell levels increases, cell-to-cell interference (C2CI) which shifts threshold voltage may degrades the error rate in reading process. There are several approaches to alleviate the errors caused by the threshold voltage shift and we discuss error correcting codes and message encoding schemes. First, we propose error correcting codes that are effective for multi-level cell flash memory and non-binary WOM (write once memory) codes. In particular, we focus on bidirectional error correction codes. The errors in MLC flash memories tend to be directional and limited-magnitude. Many related works focus on asymmetric errors, but bidirectional errors also occur because of the bidirectional interference and the adjustment of the hard-decision reference voltages. The code treats both upward and downward errors when the error magnitude in each direction differs. The maximum magnitudes of the upward error and downward error are lu and ld, respectively. One of proposed codes extends the technique of the distinct sum sets to the bidirectional error correction codes. The other code is bidirectional limited magnitude error correction codes based on modulo operation and uses non-binary conventional error correction codes. These proposed codes can reduce the parity size, and have better error correction performance than the conventional error correction codes when the code rate is equal. Furthermore, error correcting schemes for non-binary WOM codes are discussed. WOM codes is a coding scheme that allows information to be written in a memory cell multiple times without erasure, and conventional error correction codes cannot be directly applied to WOM codes. The advantages of the proposed methods are that these are practical and systematic codes, and the complexity of encoding and decoding processes are low. We also introduce effective error locating limited-magnitude parity check error correction codes for the MLC flash memory error with lower complexity. Second, we introduce coding schemes to lower the generated interferences by cell to cell interference. It is known that C2CI is caused by the threshold voltage change of neighbor cells in writing operation. The amount of threshold voltage change is proportional to the magnitude. To minimize the generated interference, the average magnitude needs to be decreased. We propose two new C2CI reduction coding schemes that adjust the average magnitude to reduce C2CI. The proposed coding scheme deals with q-ary message codes, and generates fixed length codes. Message codewords are divided into several blocks, and are modified by modulo addition with proper values to minimize the average magnitude. We also propose low energy Huffman codes based on entropy coding when the frequency of symbols is not distributed uniformly. This scheme produces variable-length codes without redundancy. We modified Huffman codes to minimize average number of high bits ('1' bits). We show that proposed codes generate optimal codewords which have minimum high bits with minimum average codeword length.Chapter 1 Introduction 1 1.1 Backgrounds 1 1.2 Scope and Organization 5 Chapter 2 MLC Flash Memory Interference and Mitigation Techniques for Reliability 9 2.1 MLC flash memory and interference 9 2.2 Signal processing based interference mitigation in MLC flash memories 15 2.3 WOM codes 22 2.4 Asymmetric limited-magitude error correction codes based on distinct sum set 27 Chapter 3 Error Correction Codes for Flash Memories 29 3.1 Introduction 29 3.2 Bidirectional error correction codes for non-binary WOM codes based on distinct sum sets 30 3.2.1 Bidirectional error correction codes based on distinct sum sets 30 3.2.2 Error correction coding schemes for WOM codes based on distinct sum sets 41 3.3 Bidirectional error correction codes for WOM codes based on modulo operation 44 3.3.1 Bidirectional error correction codes based on modulo operation 44 3.3.2 Performance simulation of bidirectional error correction codes based on modulo operation 54 3.3.3 Error correction coding schemes for WOM codes based on modulo operation 58 3.4 Performance of error correction coding schemes for WOM code 61 3.5 Error locating parity check codes for errors with limited magnitude 68 3.6 Summary 77 Chapter 4 On Interference Mitigating Codes for Multi-level Flash Memories 79 4.1 Introduction 79 4.2 The modeling of generated interference in flash memory 80 4.3 Coding schemes for interference mitigation 83 4.3.1 Minimum energy coding 83 4.3.2 Module shift coding 85 4.3.3 Low energy Huffman code 89 4.4 Performance analysis of proposed coding schemes 91 4.4.1 Performance analysis of ME codes 91 4.4.2 Performance analysis of MS codes 93 4.4.3 Performance of low-energy Huffman codes 97 4.4.4 C2CI reduction performance 99 4.5 Summary 102 Chapter 5 Conclusions 105 Appendix A 109 A.1 Performance analysis of MS coding with eta=2 case in chap. 4.4.2. 109 Bibliography 113 Abstract in Korean 120Docto

Algorithms and Data Representations for Emerging Non-Volatile Memories

The evolution of data storage technologies has been extraordinary. Hard disk drives that fit in current personal computers have the capacity that requires tons of transistors to achieve in 1970s. Today, we are at the beginning of the era of non-volatile memory (NVM). NVMs provide excellent performance such as random access, high I/O speed, low power consumption, and so on. The storage density of NVMs keeps increasing following Moore’s law. However, higher storage density also brings significant data reliability issues. When chip geometries scale down, memory cells (e.g. transistors) are aligned much closer to each other, and noise in the devices will become no longer negligible. Consequently, data will be more prone to errors and devices will have much shorter longevity. This dissertation focuses on mitigating the reliability and the endurance issues for two major NVMs, namely, NAND flash memory and phase-change memory (PCM). Our main research tools include a set of coding techniques for the communication channels implied by flash memory and PCM. To approach the problems, at bit level we design error correcting codes tailored for the asymmetric errors in flash and PCM, we propose joint coding scheme for endurance and reliability, error scrubbing methods for controlling storage channel quality, and study codes that are inherently resisting to typical errors in flash and PCM; at higher levels, we are interested in analyzing the structures and the meanings of the stored data, and propose methods that pass such metadata to help further improve the coding performance at bit level. The highlights of this dissertation include the first set of write-once memory code constructions which correct a significant number of errors, a practical framework which corrects errors utilizing the redundancies in texts, the first report of the performance of polar codes for flash memories, and the emulation of rank modulation codes in NAND flash chips

Efficient Two-Write WOM-Codes

A Write Once Memory (WOM) is a storage medium with binary memory elements, called cells, that can change from the zero state to the one state only once. Examples of WOMs are punch cards, optical disks, and more recently flash memories. A t-write WOM-code is a coding scheme for storing t messages in n cells in such a way that each cell can change its value only from the zero state to the one state. The WOM-rate of a t-write WOM-code is the ratio of the total amount of information written to the WOM in t writes to the number of cells. In this paper we present a family of 2-write WOM-codes. It is shown how to construct from each linear code C a 2-write WOMcode. Then, we find 2-write WOM-codes that improve the best known WOM-rate with two writes. This scheme is proved to be capacity achieving when the parity check matrix of the linear code C is chosen uniformly at random. Finally, we show how to take advantage of 2-write WOM-codes in order to construct codes for the Blackwell channel