Fast algorithm for the 3-D DCT-II

Recently, many applications for three-dimensional (3-D) image and video compression have been proposed using 3-D discrete cosine transforms (3-D DCTs). Among different types of DCTs, the type-II DCT (DCT-II) is the most used. In order to use the 3-D DCTs in practical applications, fast 3-D algorithms are essential. Therefore, in this paper, the 3-D vector-radix decimation-in-frequency (3-D VR DIF) algorithm that calculates the 3-D DCT-II directly is introduced. The mathematical analysis and the implementation of the developed algorithm are presented, showing that this algorithm possesses a regular structure, can be implemented in-place for efficient use of memory, and is faster than the conventional row-column-frame (RCF) approach. Furthermore, an application of 3-D video compression-based 3-D DCT-II is implemented using the 3-D new algorithm. This has led to a substantial speed improvement for 3-D DCT-II-based compression systems and proved the validity of the developed algorithm

Frontoparietal action-oriented codes support novel task set implementation

A key aspect of human cognitive flexibility concerns the ability to rapidly convert complex symbolic instructions into novel behaviors. Previous research proposes that this fast configuration is supported by two differentiated neurocognitive states, namely, an initial declarative maintenance of task knowledge, and a progressive transformation into a pragmatic, action-oriented state necessary for optimal task execution. Furthermore, current models predict a crucial role of frontal and parietal brain regions in this transformation. However, direct evidence for such frontoparietal formatting of novel task representations is still lacking. Here, we report the results of an fMRI experiment in which participants had to execute novel instructed stimulus-response associations. We then used a multivariate pattern-tracking procedure to quantify the degree of neural activation of instructions in declarative and procedural representational formats. This analysis revealed, for the first time, format-unique representations of relevant task sets in frontoparietal areas, prior to execution. Critically, the degree of procedural (but not declarative) activation predicted subsequent behavioral performance. Our results shed light on current debates on the architecture of cognitive control and working memory systems, suggesting a contribution of frontoparietal regions to output gating mechanisms that drive behavior

A VLSI architecture of JPEG2000 encoder

Copyright @ 2004 IEEEThis paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). For DWT, a spatial combinative lifting algorithm (SCLA)-based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations, respectively, compared with the conventional lifting-based implementation (LBI). For EBCOT, a dynamic memory control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed up the EBCOT context formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bitstream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the rate-distortion (RD) truncation.This work was supported in part by the China National High Technologies Research Program (863) under Grant 2002AA1Z142