Design of a 5-bit algorithmic A/D converter for potential use in a wireless neural recorder application

The constant endeavor to measure and record neural signals from the human brain and anticipate the results to figure out the mechanism which governs the functionality of our brain and its true behavior is the major driving force behind this thesis. Neural recording integrated circuits (ICs) are often inserted directly into the brain, with a set of probes for sensing these action potentials (and local field potentials), and appropriate circuitry for amplifying the neural signals (Pre-Amp), sampling and converting the analog signals to digital (ADC) and transmitting the resulting digital signal (Transmitter) to a nearby reader instrument (Receiver). Action potentials are comprised of signals typically looking like spikes having a peak voltage of 1-2mV, whereas local field potentials are continuous signals generally having an amplitude of around 100-200μV often with a dc component of several mV. Fourier analysis of action potentials and local field potentials show frequency components in the range of 0.1 Hz up to 10kHz. This thesis proposes a low-power 5-bit algorithmic A/D converter to feed a 5-stage serial shift register for use in sampling and converting a presumed neuron action potential signal at the rate of 20k samples/sec. In addition to that, a low-power preamp with at least 40dB gain and a low-pass type spectrum having a unity-gain frequency of at least 20MHz is used to amplify the input signal. The algorithmic A/D converter includes a sample-and-hold circuit for sampling the analog action potential spike at a rate of 20kHz. The ADC utilizes an X2 gain circuit based on a capacitive redistribution technique. A less complex circuit in terms of dependency on Capacitor sizing and their non-ideal effects is the key factor for selecting this type of ADC which can be used for neural recording applications. All the circuits are designed based on the IBM/Global Foundries 8HP 130nm BiCMOS technology

Efficient Error-Cancelling Algorithmic ADC

An algorithmic ADC that is insensitive to capacitor mismatch and finite opamp gain and offset is described. Using the differential sampling scheme with the correlated double sampling (CDS) technique together, the virtually errorfree and fast multiply-by-two operation is obtained for the proposed ADC. For an N-bit converter, a new output word is obtained every 4N clock periods, and this represents a significant improvement in conversion speed (or efficiency) in comparison to the latest work to achieve the same error compensation. Thus it can be used in the applications which require low-cost medium-speed and high-resolution A/D conversion. 1