Hyperreconfigurable architectures as flexible control systems

Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing flexibility of modern dynamically reconfigurable systems improves their adaptability but also makes fast reconfiguration difficult because of the large amount of necessary reconfiguration information. However, even when a computation uses this flexibility it will not use it all the time. Therefore, we propose to make the potential for reconfigurationitself reconfigurable. This allows for speeding up reconfiguration operations during phases where only parts of the total flexibility are required. Such architectures are called hyperreconfigurable and use two types of reconfiguration operations: hyperreconfigurations for changing the reconfiguration potential and ordinary reconfigurations for actually configuring a new context for a computation

The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures

Hyperreconfigurable architectures adapt their reconfiguration abilities during run time in order to achieve fast dynamic reconfiguration. Models for such architectures have been proposed that change their ability for reconfiguration during hyperreconfiguration steps and in ordinary reconfiguration steps reconfigure the actual contexts for a computation within the limits that have been set by the last hyperreconfiguration step. In this paper we study algorithmic aspects of how to optimally decide what hyperreconfiguration steps should be done during a computation in order to minimize the total time necessary for hyperreconfiguration and ordinary reconfiguration. It is shown that the general problem is NP-hard but fast polynomial time algorithms are given to solve this problem on different types of hyperreconfigurable architectures. These include newly introduced architectures that use a cache to store hypercontexts. We define an example hyperreconfigurable architecture and illustrate the introduced concepts for three application problems

Hyperreconfigurable architectures and the partition into hypercontexts problem

Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit the changing needs of a computation during run time. The increasing flexibility of modern dynamically reconfigurable systems improves their adaptability to computational needs but also makes fast reconfiguration difficult because of the large amount of reconfiguration information which has to be transferred. However, even when a computation uses this flexibility it will not use it all the time. Therefore, we propose to make the potential for reconfiguration itself reconfigurable. Such architectures are called hyperreconfigurable. Different models of hyperreconfigurable architectures are proposed in this paper. We also study a fundamental problem that emerges on such architectures, namely, to determine for a given computation when and how the potential for reconfiguration should be changed during run time so that the reconfiguration overhead is minimal. It is shown that the general problem is NP-hard but fast polynomial time algorithms are given to solve this problem for special types of hyperreconfigurable architectures. We define two example hyperreconfigurable architectures and illustrate the introduced concepts for corresponding application problems

Models and reconfiguration problems for multi task hyperreconfigurable architectures

Hyperreconfigurable architectures can adapt their reconfiguration abilities during run time and have been proposed to increase the speed of dynamic reconfiguration. They use two types of dynamic reconfiguration steps. In hyperreconfiguration steps they change their ability for reconfiguration and in ordinary reconfiguration steps they reconfigure the actual contexts for a computation within the limits that have been set by the last hyperreconfiguration step. We study the concept of partial hyperreconfiguration for multi tasks environments. We propose several models for partially hyperreconfigurable architectures and study corresponding reconfiguration problems to find optimal (hyper)reconfigurations. While under a general cost model the problem to find optimal (hyper)reconfigurations is known to be NP-complete even for a single task. We identify an interesting special case that can be solved by a polynomial time algorithm even for multiple tasks. We illustrate the introduced concepts with a partially hyperreconfigurable example architecture and describe the results of simulated runs with a small test application

A Reconfigurable Pattern Matching Hardware Implementation Using On-Chip Ram-Based FSM

The use of synthesizable reconfigurable IP cores has increasingly become a trend in System on Chip (SOC) designs. Such domain-special cores are being used for their flexibility and powerful functionality. The market introduction of multi-featured platform FPGAs equipped with on-chip memory and embedded processor blocks has further extended the possibility of utilizing dynamic reconfiguration to improve overall system adaptability to meet varying product requirements. A dynamically reconfigurable Finite State Machine (FSM) can be implemented using on-chip memory and an embedded processor. Since FSMs are the vital part of sequential hardware designs, the reconfiguration can be achieved in all designs containing FSMs. In this thesis, a FSM-based reconfigurable hardware implementation is presented. The embedded soft-core processor is used for orchestrating the run-time reconfiguration. The FSM is implemented using an on-chip memory. The hardware can be reconfigured on-the-fly by only altering the memory content. The use of a processor for reconfiguration enables SOC designers to utilize both software and hardware capability to achieve reconfiguration. This scheme of reconfigurable hardware implementation is independent of the placement and routing of the hardware on the FPGA. To demonstrate the feasibility of the proposed approach, the Knuth-Morris-Pratt (KMP) algorithm was implemented. A unique way of using memory-based FSM to reconfigure and speed up the KMP search algorithm has been introduced. With the proposed technique, the system can reconfigure itself based on a new incoming pattern and perform a pattern search on a given text without involving a host processor. Data extracted from test cases shows that the proposed approach made the maximum achievable frequency of the design independent of the pattern length. The number of clock cycles required to match the pattern in the worst case is equal to the pattern length plus the text length (O (m+n))